公开(公告)号：US20190148506A1

公开(公告)日：2019-05-16

申请号：US15813579

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka Krishna KANAKAMEDALA ,  Yoshihiro KANNO ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Jin LIU ,  Murshed CHOWDHURY ,  Yao-Sheng LEE

IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L29/66 ,  H01L29/49

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US20180138189A1

公开(公告)日：2018-05-17

申请号：US15354067

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Murshed CHOWDHURY ,  Jin LIU ,  Johann ALSMEIER

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02494 ,  H01L21/02587 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/41741 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/518

Abstract: A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

公开(公告)号：US20190148392A1

公开(公告)日：2019-05-16

申请号：US15813625

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshihiro KANNO ,  Senaka Krishna KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Jin LIU ,  Murshed CHOWDHURY

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US20170179154A1

公开(公告)日：2017-06-22

申请号：US15269294

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoko FURIHATA ,  Jixin YU ,  Hiroyuki OGAWA ,  James KAI ,  Jin LIU ,  Johann ALSMEIER

IPC: H01L27/115 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US20170236835A1

公开(公告)日：2017-08-17

申请号：US15434544

申请日：2017-02-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi NAKAMURA ,  Jin LIU ,  Kazuya TOKUNAGA ,  Marika GUNJI-YONEOKA ,  Matthias BAENNINGER ,  Hiroyuki KINOSHITA ,  Murshed CHOWDHURY ,  Jiyin XU ,  Dai IWATA ,  Hiroyuki OGAWA ,  Kazutaka YOSHIZAWA ,  Yasuaki YONEMOCHI

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L29/788 ,  H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11526 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L21/764 ,  H01L23/29 ,  H01L23/31 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/764 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/528 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42372

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

公开(公告)号：US20170148811A1

公开(公告)日：2017-05-25

申请号：US15354116

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tong ZHANG ,  Johann ALSMEIER ,  James KAI ,  Jin LIU ,  Yanli ZHANG

IPC: H01L27/115 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L28/00

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.