公开(公告)号：US20240015963A1

公开(公告)日：2024-01-11

申请号：US17811145

申请日：2022-07-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi NAKAMURA ,  Nobuyuki FUJIMURA

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word line electrically conductive layers and a first select-level electrically conductive layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel. A vertical cross-sectional profile of an outer sidewall of the vertical semiconductor channel is straight throughout the word line electrically conductive layers and contains a lateral protrusion at a level of the first select-level electrically conductive layer.

公开(公告)号：US20240147723A1

公开(公告)日：2024-05-02

申请号：US18351181

申请日：2023-07-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Motoo OHAGA ,  Tadashi NAKAMURA ,  Takashi YUDA ,  Nobuyuki FUJIMURA ,  Hiroyuki OGAWA

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory device includes source-level material layers including a source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers, a memory opening vertically extending through the alternating stack and the source contact layer, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel including an intrinsic or first conductivity type semiconductor material, a memory film surrounding the vertical semiconductor channel, and a conical source pedestal in contact with the source contact layer and in contact with a bottom surface of the vertical semiconductor channel, such that at least portion of the conical source pedestal includes a second conductivity type semiconductor material.

公开(公告)号：US20180006049A1

公开(公告)日：2018-01-04

申请号：US15704370

申请日：2017-09-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi INOMATA ,  Nobuo HIRONAGA ,  Junichi ARIYOSHI ,  Tadashi NAKAMURA

IPC: H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11556 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

Abstract: A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.

公开(公告)号：US20210036003A1

公开(公告)日：2021-02-04

申请号：US16526128

申请日：2019-07-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jayavel PACHAMUTHU ,  Hiroyuki KINOSHITA ,  Marika GUNJI-YONEOKA ,  Tadashi NAKAMURA ,  Tomohiro OGINOE

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/45 ,  H01L29/167 ,  H01L29/04 ,  H01L21/28 ,  H01L21/02 ,  H01L21/285

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion. A connection strap is formed by performing a selective semiconductor deposition process that grows a strap semiconductor material from a physically exposed surface of an underlying semiconductor material portion through the opening. A vertical semiconductor channel is formed on an inner sidewall of the memory film by non-selectively depositing a semiconductor channel material. The connection strap provides an electrical connection between the underlying semiconductor material portion and the vertical semiconductor channel through the opening in the memory film. The sacrificial material layers are then replaced with electrically conductive layers.

公开(公告)号：US20170271261A1

公开(公告)日：2017-09-21

申请号：US15183195

申请日：2016-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Kota FUNAYAMA ,  Ryoichi EHARA ,  Youko FURIHATA ,  Zhenyu LU ,  Tong ZHANG ,  Tadashi NAKAMURA

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of forming a monolithic three-dimensional memory device includes forming a first alternating stack over a substrate, forming an insulating cap layer, forming a first memory opening through the insulating cap layer and the first alternating stack, forming a sacrificial pillar structure in the first memory opening, forming a second alternating stack, forming a second memory opening, forming an inter-stack memory opening, forming a memory film and a first semiconductor channel layer in the inter-stack memory opening, anisotropically etching a horizontal bottom portion of the memory film and the first semiconductor channel layer to expose the substrate at the bottom of the inter-stack memory opening such that damage to portions of the first semiconductor channel layer and the memory film located adjacent to the insulating cap layer is reduced or avoided, and forming a second semiconductor channel layer in contact with the exposed substrate in the inter-stack memory opening.

公开(公告)号：US20170236835A1

公开(公告)日：2017-08-17

申请号：US15434544

申请日：2017-02-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi NAKAMURA ,  Jin LIU ,  Kazuya TOKUNAGA ,  Marika GUNJI-YONEOKA ,  Matthias BAENNINGER ,  Hiroyuki KINOSHITA ,  Murshed CHOWDHURY ,  Jiyin XU ,  Dai IWATA ,  Hiroyuki OGAWA ,  Kazutaka YOSHIZAWA ,  Yasuaki YONEMOCHI

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L29/788 ,  H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11526 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L21/764 ,  H01L23/29 ,  H01L23/31 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/764 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/528 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42372

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.