公开(公告)号：US20170271261A1

公开(公告)日：2017-09-21

申请号：US15183195

申请日：2016-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Kota FUNAYAMA ,  Ryoichi EHARA ,  Youko FURIHATA ,  Zhenyu LU ,  Tong ZHANG ,  Tadashi NAKAMURA

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of forming a monolithic three-dimensional memory device includes forming a first alternating stack over a substrate, forming an insulating cap layer, forming a first memory opening through the insulating cap layer and the first alternating stack, forming a sacrificial pillar structure in the first memory opening, forming a second alternating stack, forming a second memory opening, forming an inter-stack memory opening, forming a memory film and a first semiconductor channel layer in the inter-stack memory opening, anisotropically etching a horizontal bottom portion of the memory film and the first semiconductor channel layer to expose the substrate at the bottom of the inter-stack memory opening such that damage to portions of the first semiconductor channel layer and the memory film located adjacent to the insulating cap layer is reduced or avoided, and forming a second semiconductor channel layer in contact with the exposed substrate in the inter-stack memory opening.

公开(公告)号：US20180122906A1

公开(公告)日：2018-05-03

申请号：US15458272

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin YU ,  Kento KITAMURA ,  Tong ZHANG ,  Chun GE ,  Yanli ZHANG ,  Satoshi SHIMIZU ,  Yasuo KASAGI ,  Hiroyuki OGAWA ,  Daxin MAO ,  Kensuke YAMAGUCHI ,  Johann ALSMEIER ,  James KAI

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

公开(公告)号：US20190027488A1

公开(公告)日：2019-01-24

申请号：US15818061

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Johann ALSMEIER ,  Shinsuke YADA ,  Akihisa SAI ,  Sayako NAGAMINE ,  Takashi ORIMOTO ,  Tong ZHANG

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

公开(公告)号：US20170236896A1

公开(公告)日：2017-08-17

申请号：US15155639

申请日：2016-05-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhenyu LU ,  Kota FUNAYAMA ,  Chun-Ming WANG ,  Jixin YU ,  Chenche HUANG ,  Tong ZHANG ,  Daxin MAO ,  Johann ALSMEIER ,  Makoto YOSHIDA ,  Lauren MATSUMOTO

IPC: H01L29/06 ,  H01L27/115

CPC classification number: H01L29/0649 ,  H01L27/1128 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481

Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.

公开(公告)号：US20170148811A1

公开(公告)日：2017-05-25

申请号：US15354116

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tong ZHANG ,  Johann ALSMEIER ,  James KAI ,  Jin LIU ,  Yanli ZHANG

IPC: H01L27/115 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L28/00

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.