公开(公告)号：US20200286907A1

公开(公告)日：2020-09-10

申请号：US16882957

申请日：2020-05-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun GE ,  Yanli ZHANG ,  Fei ZHOU ,  Raghuveer S. MAKALA

IPC: H01L27/11568 ,  H01L29/51 ,  H01L29/792 ,  H01L27/1159 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

公开(公告)号：US20200235116A1

公开(公告)日：2020-07-23

申请号：US16251854

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun GE ,  Yanli ZHANG ,  Fei ZHOU ,  Raghuveer S. MAKALA

IPC: H01L27/11568 ,  H01L27/1159 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H01L29/51 ,  H01L21/28

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

公开(公告)号：US20180122906A1

公开(公告)日：2018-05-03

申请号：US15458272

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin YU ,  Kento KITAMURA ,  Tong ZHANG ,  Chun GE ,  Yanli ZHANG ,  Satoshi SHIMIZU ,  Yasuo KASAGI ,  Hiroyuki OGAWA ,  Daxin MAO ,  Kensuke YAMAGUCHI ,  Johann ALSMEIER ,  James KAI

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

公开(公告)号：US20180197876A1

公开(公告)日：2018-07-12

申请号：US15401426

申请日：2017-01-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun GE ,  Yanli ZHANG ,  Johann ALSMEIER ,  Fabo YU ,  Jixin YU

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses. At least an outer portion of the laterally protruding semiconductor portion can be oxidized to form a tubular semiconductor oxide spacer. Electrically conductive layers can be formed in the backside recesses to provide word lines for a three-dimensional memory device.

公开(公告)号：US20170352678A1

公开(公告)日：2017-12-07

申请号：US15175450

申请日：2016-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhenyu LU ,  Jixin YU ,  Johann ALSMEIER ,  Fumiaki TOYAMA ,  Yuki MIZUTANI ,  Hiroyuki OGAWA ,  Chun GE ,  Daxin MAO ,  Yanli ZHANG ,  Alexander CHU ,  Yan LI

IPC: H01L27/11582 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L27/11582 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49844 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region. At least one through-memory-level via structure can be formed through the remaining portions of the spacer dielectric layers and the insulating layers to provide a vertically conductive path through a memory-level assembly.