公开(公告)号：US09679835B2

公开(公告)日：2017-06-13

申请号：US14741827

申请日：2015-06-17

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Shinya Kubota ,  Masaru Akino

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L23/49582 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A resin-encapsulated semiconductor device comprises a semiconductor chip mounted on a die pad. A plurality of leads each having an inner lead and an outer lead are arranged in spaced relation from the die pad with the inner leads facing the die pad. A metal plating layer is formed on top surfaces of the inner leads, and the inner leads are connected by metal wires to the semiconductor chip. An encapsulation resin encapsulates the semiconductor chip, die pad, metal wires and inner leads leaving the outer leads exposed. The outer edge of the metal plating layer coincides with the outer surface of the encapsulation resin and with the outer edge of the metal plating layer.

公开(公告)号：US09437669B2

公开(公告)日：2016-09-06

申请号：US14617572

申请日：2015-02-09

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hirofumi Harada ,  Masaru Akino

IPC: H01L27/10 ,  H01L49/02 ,  H01L27/08

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: A semiconductor resistor circuit has resistor elements of a polycrystalline silicon thin film formed on an insulating film deposited on a semiconductor substrate. A high stress insulating film is formed on and covers the resistor elements and the insulating film exposed between the resistor elements. Metal wirings cover upper portions of the resistor elements. The high stress insulating film has a membrane stress that is higher than that of the metal wirings.

Abstract translation: 半导体电阻电路具有形成在沉积在半导体衬底上的绝缘膜上的多晶硅薄膜的电阻元件。 在电阻元件和电阻元件之间露出的绝缘膜上形成并覆盖高应力绝缘膜。 金属布线覆盖电阻元件的上部。 高应力绝缘膜的膜应力高于金属配线。

公开(公告)号：US09184116B2

公开(公告)日：2015-11-10

申请号：US14174722

申请日：2014-02-06

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Shinya Kubota ,  Masaru Akino

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49582 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a resin-encapsulated semiconductor device capable of supporting finer pitches comprises forming a metal plating layer on an inner lead and an outer lead of a lead. A semiconductor chip is mounted on a die pad, and an electrode on a surface of the semiconductor chip is electrically connected to the inner lead via a thin metal wire. The semiconductor chip, the thin metal wire and the inner lead are encapsulated by an encapsulation resin so that the outer lead extends beyond the encapsulation resin and is exposed. Resin burrs formed during resin encapsulation are removed by a defocused laser, and any metal adhered on the lead is lifted off.

Abstract translation: 一种制造能够支撑更细的间距的树脂封装的半导体器件的方法包括在引线的内引线和外引线上形成金属镀层。 半导体芯片安装在芯片焊盘上，并且半导体芯片的表面上的电极经由薄金属线电连接到内引线。 半导体芯片，细金属丝和内部引线被封装树脂封装，使得外部引线延伸超过封装树脂并暴露。 通过散焦的激光去除在树脂封装期间形成的树脂毛刺，并且将附着在引线上的任何金属剥离。

公开(公告)号：US09945912B2

公开(公告)日：2018-04-17

申请号：US14943509

申请日：2015-11-17

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Takaaki Hioka ,  Masaru Akino

IPC: G01R33/00 ,  G01R33/07

CPC classification number: G01R33/0017 ,  G01R33/007 ,  G01R33/07

Abstract: In a Hall sensor in which a Hall element and elements serving as heat sources out of components of a circuit for driving the Hall element are arranged close to each other on a silicon substrate, two directions of control currents by spinning current for the Hall element are selected in a vector manner based on signals from temperature sensors arranged close to a periphery of the Hall element, thereby enabling the elimination of a magnetic offset caused by heat generation of the heat sources.

公开(公告)号：US09296142B2

公开(公告)日：2016-03-29

申请号：US14494664

申请日：2014-09-24

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Yasuo Terui ,  Masaru Akino

IPC: B29C45/14 ,  H01L21/56 ,  B29C45/40 ,  B29L31/34

CPC classification number: B29C45/14065 ,  B29C45/14655 ,  B29C45/32 ,  B29C45/401 ,  B29C2045/14147 ,  B29K2101/10 ,  B29K2101/12 ,  B29L2031/3406 ,  B29L2031/3481 ,  H01L21/565 ,  H01L2224/48091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device manufacturing apparatus for encapsulating with a resin a semiconductor chip. A lead frame on which the semiconductor chip is mounted is provided between an upper mold and a lower mold. A tapered positioning pin is provided to the lower mold and includes a columnar portion having an outer diameter larger than an inner diameter of a positioning hole provided at an upper surface of the lead frame and configured to receive the columnar portion of the tapered positioning pin. Ejector pins are disposed in proximity to the tapered positioning pin at a distance determined by a thickness of the lead frame. The ejector pins are arranged so as to be symmetrical with respect to the tapered positioning pin.

Abstract translation: 一种用树脂封装半导体芯片的半导体器件制造装置。 在上模和下模之间设置有安装半导体芯片的引线框架。 锥形定位销设置在下模具上，并且包括一个柱形部分，其外径大于设置在引线框架的上表面处的定位孔的内径，并被构造成容纳锥形定位销的柱形部分。 顶针设置在锥形定位销附近，距离由引线框架的厚度确定。 排出销布置成相对于锥形定位销对称。

公开(公告)号：US09362195B2

公开(公告)日：2016-06-07

申请号：US14319414

申请日：2014-06-30

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Koji Tsukagoshi ,  Sadao Oku ,  Hiroyuki Fujita ,  Keiichiro Hayashi ,  Masaru Akino

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L23/24

CPC classification number: H01L23/3114 ,  H01L23/24 ,  H01L23/49551 ,  H01L23/49861 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00012

Abstract: Provided is a semiconductor device including a package having a hollow portion, which can meet the need of reduction in size and thickness. The semiconductor device includes: a resin molded member (1) including a hollow portion (10) having an inner bottom surface on which a semiconductor chip (6) is mounted, a surrounding portion (1b) that surrounds the hollow portion (10), and a bottom surface portion (1a); an inner lead (2e, 2f); and an outer lead (2a, 2b) exposed from the resin molded member (1). The inner lead buried in the molded member (1) includes an L-shaped lead extending portion having a through hole formed therethrough.

Abstract translation: 提供一种包括具有中空部分的封装的半导体器件，其可以满足尺寸和厚度的减小的需要。 半导体装置包括：具有中空部（10）的树脂成形体（1），具有安装有半导体芯片（6）的内底面，围绕中空部（10）的环绕部（1b） 和底面部分（1a）; 内引线（2e，2f）; 和从树脂成形体（1）露出的外引线（2a，2b）。 埋在模制构件（1）中的内部引线包括具有穿过其形成的通孔的L形引线延伸部分。

公开(公告)号：US09117799B2

公开(公告)日：2015-08-25

申请号：US14203935

申请日：2014-03-11

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Masaru Akino

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/43 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05198 ,  H01L2224/052 ,  H01L2224/05395 ,  H01L2224/43 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00

Abstract: In a method of manufacturing semiconductor device, an insulating film is provided on a surface of a semiconductor substrate, a porous metal film containing numerous voids is formed on a region of the insulating film, and a protective film is provided on the porous metal film. The protective film is provided with an opening portion on the porous metal film, with the opening portion defining a pad region. A wire is wire-bonded to the porous metal film in the pad region.

Abstract translation: 在制造半导体器件的方法中，在半导体衬底的表面上设置绝缘膜，在绝缘膜的区域上形成含有多个空隙的多孔金属膜，并在多孔金属膜上设置保护膜。 保护膜在多孔金属膜上设置有开口部分，开口部分限定了焊盘区域。 导线与焊盘区域中的多孔金属膜引线接合。