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    IMAGE SENSORS WITH IMPROVED SURFACE PLANARITY
    1.
    发明申请
    IMAGE SENSORS WITH IMPROVED SURFACE PLANARITY 有权

    公开(公告)号：US20170141146A1

    公开(公告)日：2017-05-18

    申请号：US15139505

    申请日：2016-04-27

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Aaron BELSHER ,  Richard MAURITZSON ,  Swarnal BORTHAKUR ,  Ulrich BOETTIGER

    IPC: H01L27/146

    CPC classification number: H01L27/14603 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

    Abstract: A backside illuminated image sensor with an array of pixels formed in a substrate is provided. To improve surface planarity, bond pads formed at the periphery of the array of pixels may be recessed into a back surface of the substrate. The bond pads may be recessed into a semiconductor layer of the substrate, may be recessed into a window in the semiconductor layer, or may be recessed in a passivation layer and covered with non-conductive material such as resin. In order to further improve surface planarity, a window may be formed in the semiconductor layer at the periphery of the array of pixels, or scribe region, over alignment structures. By providing an image sensor with improved surface planarity, device yield and time-to-market may be improved, and window framing defects and microlens/color filter non-uniformity may be reduced.

    SEMICONDUCTOR DEVICES WITH SINGLE-PHOTON AVALANCHE DIODES AND ISOLATION STRUCTURES
    2.
    发明申请
    SEMICONDUCTOR DEVICES WITH SINGLE-PHOTON AVALANCHE DIODES AND ISOLATION STRUCTURES 有权

    公开(公告)号：US20220367534A1

    公开(公告)日：2022-11-17

    申请号：US17302836

    申请日：2021-05-13

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jeffrey Peter GAMBINO ,  David T. PRICE ,  Marc Allen SULFRIDGE ,  Richard MAURITZSON ,  Michael Gerard KEYES ,  Ryan RETTMANN ,  Kevin MCSTAY

    IPC: H01L27/146

    Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

    HIGH DYNAMIC RANGE PIXEL USING LIGHT SEPARATION
    3.
    发明申请
    HIGH DYNAMIC RANGE PIXEL USING LIGHT SEPARATION 审中-公开

    公开(公告)号：US20180269245A1

    公开(公告)日：2018-09-20

    申请号：US15758387

    申请日：2016-12-08

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Marko MLINAR ,  Ulrich BOETTIGER ,  Richard MAURITZSON

    IPC: H01L27/146 ,  H04N5/369 ,  H04N9/04

    CPC classification number: H01L27/14621 ,  H01L27/14607 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14645 ,  H04N5/3696 ,  H04N9/04

    Abstract: An image sensor may include pixels having nested sub-pixels. A pixel with nested sub-pixels may include an inner sub-pixel that has either an elliptical or a rectangular light collecting area. The inner sub-pixel may be formed in a substrate and may be immediately surrounded by a sub-pixel group that includes one or more sub-pixels. The inner sub-pixel may have a light collecting area at a surface that is less sensitive than the light collecting area of the one or more outer sub-pixel groups. Microlenses may be formed over the nested sub-pixels, to direct light away from the inner sub-pixel group to the outer sub-pixel groups in nested sub-pixels. A color filter of a single color may be formed over the nested sub-pixels. Hybrid color filters having a single color filter region over the inner sub-pixel and a portion of the one or more outer sub-pixel groups may also be used.

    STACKED-DIE IMAGE SENSORS WITH SHIELDING
    5.
    发明申请
    STACKED-DIE IMAGE SENSORS WITH SHIELDING 审中-公开

    公开(公告)号：US20170221954A1

    公开(公告)日：2017-08-03

    申请号：US15155245

    申请日：2016-05-16

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Raminda MADURAWE ,  Richard MAURITZSON

    IPC: H01L27/146 ,  H01L25/04

    Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

    HIGH DYNAMIC RANGE PIXEL USING LIGHT SEPARATION
    7.
    发明申请
    HIGH DYNAMIC RANGE PIXEL USING LIGHT SEPARATION 审中-公开

    公开(公告)号：US20200020730A1

    公开(公告)日：2020-01-16

    申请号：US16583743

    申请日：2019-09-26

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Marko MLINAR ,  Ulrich BOETTIGER ,  Richard MAURITZSON

    IPC: H01L27/146 ,  H04N9/04 ,  H04N5/369

    Abstract: An image sensor may include pixels having nested sub-pixels. A pixel with nested sub-pixels may include an inner sub-pixel that has either an elliptical or a rectangular light collecting area. The inner sub-pixel may be formed in a substrate and may be immediately surrounded by a sub-pixel group that includes one or more sub-pixels. The inner sub-pixel may have a light collecting area at a surface that is less sensitive than the light collecting area of the one or more outer sub-pixel groups. Microlenses may be formed over the nested sub-pixels, to direct light away from the inner sub-pixel group to the outer sub-pixel groups in nested sub-pixels. A color filter of a single color may be formed over the nested sub-pixels. Hybrid color filters having a single color filter region over the inner sub-pixel and a portion of the one or more outer sub-pixel groups may also be used.

    ARC PREVENTION FOR BONDED WAFERS OF A CHIP STACK
    9.
    发明申请
    ARC PREVENTION FOR BONDED WAFERS OF A CHIP STACK 有权

    公开(公告)号：US20250125284A1

    公开(公告)日：2025-04-17

    申请号：US18488628

    申请日：2023-10-17

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jeffrey Peter GAMBINO ,  David T. PRICE ,  Marc Allen SULFRIDGE ,  Richard MAURITZSON ,  James Joseph STEFFES

    IPC: H01L23/60 ,  H01L23/00 ,  H01L27/146

    Abstract: A semiconductor device may include a first chip with a first wafer and a first dielectric layer, and a second chip that includes a second wafer and a second dielectric layer, the second chip having a backside surface and a frontside surface opposed to the backside surface and bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. The semiconductor device may include a die seal layer on the backside surface having a die seal ground contact in contact with the second wafer, and an electrostatic discharge path that includes the die seal layer, the die seal ground contact, a first die seal in the first dielectric layer, a second die seal in the second dielectric layer, and a hybrid bond connecting the first die seal and the second die seal through the bond line.

    CHIP STACKING WITH BOND PAD ABOVE A BONDLINE
    10.
    发明申请
    CHIP STACKING WITH BOND PAD ABOVE A BONDLINE 有权

    公开(公告)号：US20240371905A1

    公开(公告)日：2024-11-07

    申请号：US18309933

    申请日：2023-05-01

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Swarnal BORTHAKUR ,  Marc Allen SULFRIDGE ,  Jeffrey Peter GAMBINO ,  Vladimir KOROBOV ,  Richard MAURITZSON ,  David T. PRICE

    IPC: H01L27/146 ,  H01L23/58

    Abstract: A semiconductor device may include a first chip that includes a first wafer and a first dielectric layer disposed thereon. The semiconductor device may include a second chip that includes a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposed to the backside surface, the second chip being bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. An opening through the backside surface of the second chip may extend into the second dielectric layer, and a bond pad may be disposed within the second dielectric layer between the second wafer and the bond line.

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