公开(公告)号：US20200185543A1

公开(公告)日：2020-06-11

申请号：US16789499

申请日：2020-02-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed Tanvir QUDDUS ,  Mihir MUDHOLKAR ,  Jefferson W. HALL

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/47 ,  H01L27/07 ,  H01L27/095 ,  H01L29/66 ,  H01L27/02

Abstract: A method for manufacturing a semiconductor component includes forming first mesa and second mesa structures from a semiconductor material by etching trenches into the semiconductor material. A doped region having a multi-concentration dopant profile is formed in at least the first mesa structure and doped polysilicon is formed in the trenches. The trenches are formed in a geometric pattern. A contact having three contact types is formed, wherein a first contact type is formed to the first mesa structure, a second contact type is formed to the second mesa structure, and a third contact type is formed to the doped polysilicon in the trenches. The first contact type has electrical properties between a conventional Schottky contact and a conventional Ohmic contact without being a conventional Schottky contact or a conventional Ohmic contact, the second contact type is a Schottky contact, the third contact type is an Ohmic contract.

公开(公告)号：US20190288125A1

公开(公告)日：2019-09-19

申请号：US15919475

申请日：2018-03-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed Tanvir QUDDUS ,  Mihir MUDHOLKAR ,  Jefferson W. HALL

IPC: H01L29/872 ,  H01L27/02 ,  H01L27/07 ,  H01L27/095 ,  H01L29/66

Abstract: A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalls and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the dope region with the multi-concentration impurity profile.

公开(公告)号：US20210135019A1

公开(公告)日：2021-05-06

申请号：US17145607

申请日：2021-01-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed Tanvir QUDDUS ,  Mihir MUDHOLKAR ,  Zia HOSSAIN

IPC: H01L29/872 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

公开(公告)号：US20200006580A1

公开(公告)日：2020-01-02

申请号：US16529382

申请日：2019-08-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed Tanvir QUDDUS ,  Mihir MUDHOLKAR

IPC: H01L29/872 ,  H01L27/07 ,  H01L27/02 ,  H01L29/78

Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

公开(公告)号：US20190386153A1

公开(公告)日：2019-12-19

申请号：US16546049

申请日：2019-08-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed Tanvir QUDDUS ,  Mihir MUDHOLKAR ,  Michael THOMASON

IPC: H01L29/872 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes providing a region of semiconductor material comprising a major surface. A termination trench is provided extending from a first portion of the major surface into the region of semiconductor material to a first depth and has a first width. A first active trench is provided extending from a second portion of the major surface into the region of semiconductor material to a second depth and has a second width less than the first width. A second active trench is provided extending from a third portion of the major surface into the region of semiconductor material to a third depth and has a third width less than the first width. A first conductive material is provided adjoining a fourth portion of the major surface, which is configured as a Schottky barrier. The selected trench depth difference alone or in combination with other features provides a semiconductor device having improved performance characteristics.

公开(公告)号：US20170076949A1

公开(公告)日：2017-03-16

申请号：US15358361

申请日：2016-11-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael THOMASON ,  Mohammed Tanvir QUDDUS ,  James MORGAN ,  Mihir MUDHOLKAR ,  Scott DONALDSON ,  Gordon M. GRIVNA

IPC: H01L21/285 ,  H01L29/47 ,  H01L29/872 ,  H01L29/66

CPC classification number: H01L21/28537 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/76883 ,  H01L21/76889 ,  H01L29/401 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66143 ,  H01L29/8725

Abstract: A number of variations may include a method that may include depositing a first layer on a first semiconductor layer in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The first layer may include a first metal and a second metal. A second layer may comprise a material constructed and arranged to scavenge semiconductor material migrating from the first semiconductor layer during annealing may be deposited over the first layer. The first semiconductor layer may be subjected to at least a first annealing act to provide a first structure. At least a portion of the first structure may be stripped to remove any of the first layer not reacted with the semiconductor material to form a Schottky barrier structure during the first annealing act.

Abstract translation: 许多变型可以包括一种方法，其可以包括相对于形成在第一半导体外延层中的至少一个沟槽结构，在覆盖位置的第一半导体层上沉积第一层。 第一层可以包括第一金属和第二金属。 第二层可以包括构造和布置为清除在退火期间从第一半导体层迁移的半导体材料的材料可以沉积在第一层上。 可以对第一半导体层进行至少第一退火处理以提供第一结构。 可以剥离第一结构的至少一部分以去除在半导体材料中未反应的任何第一层，以在第一退火行为期间形成肖特基势垒结构。

公开(公告)号：US20200006579A1

公开(公告)日：2020-01-02

申请号：US16396446

申请日：2019-04-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed Tanvir QUDDUS ,  Mihir MUDHOLKAR ,  Zia HOSSAIN

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/40

Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

公开(公告)号：US20150325567A1

公开(公告)日：2015-11-12

申请号：US14803365

申请日：2015-07-20

Applicant: Semiconductor Components Industries, LLC

Inventor： Gordon M. GRIVNA ,  Jefferson W. HALL ,  Mohammed Tanvir QUDDUS

IPC: H01L27/02 ,  H01L29/872 ,  H01L29/10 ,  H01L29/423 ,  H01L27/06 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/402 ,  H01L29/42364 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/8725

Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.

Abstract translation: 公开了一种二极管（200），其具有改进的效率，较小的外形尺寸和减小的反向偏置漏电流。 肖特基二极管（212）形成在台面区域（206）的侧壁（210）上。 台面区域（206）是肖特基二极管（212）的阴极。 通过台面区域（206）的电流路径具有横向和垂直电流路径。 二极管（200）还包括MOS结构（214），p型区（220），MOS结构（230）和p型区（232）。 具有p型区域（220）的MOS结构（214）在反向偏压条件下夹紧横向电流路径。 P型区域（220），MOS结构（230）和p型区域（232）各自在反向偏置条件下夹紧垂直电流路径。 MOS结构（214）和MOS结构（230）在正向偏置条件下降低横向和垂直电流通路的电阻。 台面区域（206）可以具有均匀或不均匀的掺杂浓度。

公开(公告)号：US20170288027A1

公开(公告)日：2017-10-05

申请号：US15627281

申请日：2017-06-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed Tanvir QUDDUS ,  Mihir MUDHOLKAR ,  Michael THOMASON

IPC: H01L29/36

CPC classification number: H01L29/8725 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66143

Abstract: A method of forming a semiconductor includes a providing a termination trench and an active trench within a semiconductor layer. The active trench is configured to be at a shallower depth than the termination trench to provide a trench depth difference. The selected trench depth difference in combination with one or more of the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.

公开(公告)号：US20160260845A1

公开(公告)日：2016-09-08

申请号：US14640242

申请日：2015-03-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed Tanvir QUDDUS ,  Mihir MUDHOLKAR ,  Michael THOMASON

IPC: H01L29/872 ,  H01L29/66

CPC classification number: H01L29/8725 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66143

Abstract: In one embodiment, a trench Schottky rectifier includes a termination trench and active trenches provided in a semiconductor layer. A first active trench is configured to be at a shallower depth than the termination trench to provide a trench depth difference. A second active trench is configured to be at a depth similar to the termination trench. The selected trench depth difference in combination with one or more of the other second active trench depth, the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, first active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.

Abstract translation: 在一个实施例中，沟槽肖特基整流器包括端接沟槽和设置在半导体层中的有源沟槽。 第一有源沟槽被配置为处于比端接沟槽更浅的深度以提供沟槽深度差。 第二有源沟槽被配置为处于类似于端接沟槽的深度。 所选择的沟槽深度差与一个或多个另一个第二有源沟槽深度，半导体层的掺杂剂浓度，半导体层的厚度，第一有源沟槽宽度与终止沟槽宽度的一个或多个，和/或 半导体层提供具有改进的性能特性的半导体器件。