公开(公告)号：US20240194564A1

公开(公告)日：2024-06-13

申请号：US18444251

申请日：2024-02-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jihwan KIM ,  Oseob JEON ,  Seungwon IM ,  Dongwook KANG

IPC: H01L23/473 ,  H01L23/15 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/473 ,  H01L23/15 ,  H01L23/3121 ,  H01L25/0652

Abstract: In a general aspect, a semiconductor device module includes a ceramic substrate having a first surface and a second surface opposite the first surface, a patterned metal layer disposed on the first surface of the ceramic substrate, a semiconductor die disposed on the patterned metal layer, and a cooling structure disposed on the second surface of the ceramic substrate. The cooling structure includes a plurality of copper sheets defining a plurality of fluidic-cooling channels. At least one copper sheet of the plurality of copper sheets is at least one of coated or plated with a corrosion-resistant material. The module also includes a molding compound that encapsulates the ceramic substrate, the patterned metal layer and the semiconductor die. The molding compound also partially encapsulates the cooling structure, such that a fluidic interface surface of the cooling structure is exposed through the molding compound.

公开(公告)号：US20240186218A1

公开(公告)日：2024-06-06

申请号：US18491369

申请日：2023-10-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Seungwon IM ,  Jihwan KIM ,  Dongwook KANG

IPC: H01L23/433 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/433 ,  H01L23/3672 ,  H01L23/49822 ,  H01L25/0652

Abstract: In a general aspect, a semiconductor device module includes a ceramic substrate having a first surface and a second surface opposite the first surface. A patterned metal layer is disposed on the first surface of the ceramic substrate, and a semiconductor die is disposed on the patterned metal layer. A cooling structure is disposed on the second surface of the ceramic substrate, where the cooling structure includes a plurality of fluidic-cooling channels. The module also includes a molding compound that encapsulates the ceramic substrate, the patterned metal layer and the semiconductor die, and partially encapsulates the cooling structure, such that a fluidic interface surface of the cooling structure is exposed through the molding compound.

公开(公告)号：US20240363575A1

公开(公告)日：2024-10-31

申请号：US18480897

申请日：2023-10-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jihwan KIM ,  Seungwon IM ,  Oseob JEON ,  Hangil SHIN ,  Taekyun KIM

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/07 ,  H01L25/11

CPC classification number: H01L24/24 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/82 ,  H01L25/072 ,  H01L25/115 ,  H01L23/4924 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82002 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A fan out package may include a plurality of semiconductor dies, each of the semiconductor dies including a first surface and a second surface opposite to the first surface. The fan out package includes a redistribution layer coupled to the first surface of each of the plurality of semiconductor dies, a dieback conductive member coupled to the second surface of each of the plurality of semiconductors dies, and an encapsulation material coupled to the plurality of semiconductor dies and the dieback conductive member.

公开(公告)号：US20240128197A1

公开(公告)日：2024-04-18

申请号：US18487835

申请日：2023-10-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Olaf ZSCHIESCHANG ,  Oseob JEON ,  Jihwan KIM ,  Roveendra PAUL ,  Klaus NEUMAIER ,  Jerome TEYSSEYRE

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L24/24 ,  H01L24/82 ,  H01L25/072

Abstract: In a general aspect, an assembly includes a panel of organic substrate core material having a cavity defined therein, a module substrate disposed in the cavity, and a semiconductor die disposed on the module substrate. The assembly also includes a layer of prepreg organic substrate material, and a metal layer. The module substrate and the semiconductor die are embedded in the cavity by the layer of prepreg organic substrate material and the metal layer. The metal layer is electrically coupled with at least one of the semiconductor die or the module substrate.

公开(公告)号：US20230327350A1

公开(公告)日：2023-10-12

申请号：US18190725

申请日：2023-03-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON ,  Dongwook KANG ,  Youngsun KO ,  Jeungdae KIM ,  Changsun YUN ,  Jihwan KIM

IPC: H01R12/58 ,  H01R43/16 ,  H01R43/26

CPC classification number: H01R12/585 ,  H01R43/26 ,  H01R43/16

Abstract: In a general aspect, an electronic device assembly includes a substrate arranged in a plane. The substrate has a first side and a second side, the second side being opposite the first side. The assembly also includes a plurality of semiconductor die disposed on the first side of the substrate and at least one signal pin. The at least one signal pin includes a proximal end portion coupled with the first side of the substrate, a distal end portion, and a medial portion disposed between the proximal end portion and the distal end portion. The medial portion is pre-molded in a molding compound, the proximal end portion and the distal end portion exclude the molding compound. The at least one signal pin is arranged along a longitudinal axis that is orthogonal to the plane of the substrate.

公开(公告)号：US20240120253A1

公开(公告)日：2024-04-11

申请号：US18182552

申请日：2023-03-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Dongwook KANG ,  Seungwon IM ,  Jihwan KIM

IPC: H01L23/373 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495

CPC classification number: H01L23/373 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3672 ,  H01L23/49568 ,  H01L24/32 ,  H01L2224/32245

Abstract: An integrated substrate may include a conductor layer; a heat sink including a plurality of fins extending therefrom; and a dielectric layer including boron nitride chemically bonded to the conductor layer and to the heat sink with an epoxy.

公开(公告)号：US20240055334A1

公开(公告)日：2024-02-15

申请号：US18354863

申请日：2023-07-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON ,  Jihwan KIM ,  Dongwook KANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L23/3121 ,  H01L21/4853 ,  H01L21/56

Abstract: In a general aspect, an electronic device assembly includes a circuit including at least one semiconductor die, and a signal lead electrically coupled with the circuit. The signal lead has a hole defined therethrough. The assembly further includes an electrically conductive signal pin holder disposed in the hole of the signal lead. The electrically conductive signal pin holder is electrically coupled with the signal lead. The assembly also includes a molding compound encapsulating, at least, the circuit; a portion of the signal lead including the hole; and a portion of the electrically conductive signal pin holder. An open end of the electrically conductive signal pin holder is accessible outside the molding compound.