公开(公告)号：US20220262945A1

公开(公告)日：2022-08-18

申请号：US17248983

申请日：2021-02-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Tirthajyoti SARKAR

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: Diodes, transistors, and other devices having a class IV channel region and a class III-V drift region are described. The class IV channel region, such as a Si channel region, is able to provide all associated advantages, such as ease of manufacturing of many different types of devices, using cost-effective materials and techniques. Meanwhile, the III-V drift region provides substantially lower Ron_sp than a conventional class IV drift region, and substantially enhances the operational behaviors of resulting devices, without sacrificing other parameters, such as size or breakdown voltage.

公开(公告)号：US20180323273A1

公开(公告)日：2018-11-08

申请号：US15585839

申请日：2017-05-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yi SU ,  Ashok CHALLA ,  Tirthajyoti SARKAR ,  Min Kyung KO

IPC: H01L29/47 ,  H01L29/78 ,  H01L29/872 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/872 ,  H01L29/0623 ,  H01L29/407 ,  H01L29/7839 ,  H01L29/8725

Abstract: In one general aspect, a device can include a first trench disposed in a semiconductor region, a second trench disposed in the semiconductor region, and a recess disposed in the semiconductor region between the first trench and the second trench. The recess has a sidewall and a bottom surface. The device also includes a Schottky interface along a sidewall of the recess and the bottom surface of the recess excludes a Schottky interface.

公开(公告)号：US20230352577A1

公开(公告)日：2023-11-02

申请号：US18171029

申请日：2023-02-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Balaji PADMANABHAN ,  Dean E. PROBST ,  Prasad VENKATRAMAN ,  Tirthajyoti SARKAR ,  Gary Horst LOECHELT

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/66734

Abstract: An accumulation MOSFET includes a plurality of device cells. Each device cell includes a mesa adjoining a vertical trench is disposed in a doped semiconductor substrate. The mesa has a top mesa portion disposed on a bottom mesa portion. The top mesa portion has a width that is narrower than a width of the bottom mesa portion. The vertical trench adjoining the mesa has a top trench portion and a bottom trench portion. The top trench portion has a width that is wider than a width of the bottom trench portion. A dielectric is disposed on a sidewall of the vertical trench. A gate electrode disposed in the top trench portion forms an accumulation channel region in the top mesa portion and a shield electrode disposed in the bottom trench portion forms a depletion drift region in the bottom mesa portion.

公开(公告)号：US20220207351A1

公开(公告)日：2022-06-30

申请号：US17137773

申请日：2020-12-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Tirthajyoti SARKAR ,  Diann M. DOW ,  Gary Horst LOECHELT ,  Prateek SHARMA

IPC: G06N3/08 ,  G06F30/31 ,  G06F30/367 ,  G06N3/04

Abstract: According to an aspect, a semiconductor design system includes at least one neural network including a first predictive model and a second predictive model, where the first predictive model is configured to predict a first characteristic of a semiconductor device, and the second predictive model is configured to predict a second characteristic of the semiconductor device. The semiconductor design system includes an optimizer configured to use the neural network to generate a design model based on a set of input parameters, where the design model includes a set of design parameters for the semiconductor device such that the first characteristic and the second characteristic achieve respective threshold conditions.

公开(公告)号：US20210117598A1

公开(公告)日：2021-04-22

申请号：US17076039

申请日：2020-10-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph VICTORY ,  Thomas NEYER ,  YunPeng XIAO ,  Hyeongwoo JANG ,  Peter DINGENEN ,  Vaclav VALENTA ,  Tirthajyoti SARKAR ,  Mehrdad BAGHAIE YAZDI ,  Christopher Lawrence REXER ,  Stanley BENCZKOWSKI ,  Thierry BORDIGNON ,  Wai Lun CHU ,  Roman SICKARUK

IPC: G06F30/31 ,  G06F30/367 ,  G06N3/08 ,  G06N3/04

Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

公开(公告)号：US20210116888A1

公开(公告)日：2021-04-22

申请号：US17038583

申请日：2020-09-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Avery Joseph ROY ,  E. William COWELL, III ,  Luiz Henrique STIVAL ,  Tirthajyoti SARKAR ,  Robert L. BRENNAN

IPC: G05B19/4155 ,  G06N20/00 ,  G06N3/08

Abstract: Implementations of a system configured for operation of a motor may include a motor controller coupled with a memory, the motor controller configured to be coupled with a motor. The motor controller may be configured to store a set of control parameters in the memory, the set of control parameters generated using a deep reinforcement learning agent and data associated with one or more parameters of the motor. The set of control parameters may be configured to define an optimized operating area for the motor.