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    UP-DIFFUSION SUPPRESSION IN A POWER MOSFET
    1.
    发明申请
    UP-DIFFUSION SUPPRESSION IN A POWER MOSFET 有权

    公开(公告)号：US20220020851A1

    公开(公告)日：2022-01-20

    申请号：US16948806

    申请日：2020-10-01

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Prasad VENKATRAMAN

    IPC: H01L29/10 ,  H01L29/78 ,  H01L29/167 ,  H01L29/40 ,  H01L21/225 ,  H01L21/265 ,  H01L29/66

    Abstract: A substrate for fabricating a MOSFET device includes a first epitaxial layer disposed on a silicon wafer. The silicon wafer is doped with a first dopant. A second epitaxial layer is disposed on the first epitaxial layer. An ion-implanted capping layer is disposed in the first epitaxial layer. The ion-implanted capping layer is doped with a second dopant. The first dopant has a diffusion coefficient in silicon higher than a diffusion coefficient of the second dopant in silicon. The ion-implanted capping layer is configured to limit up-diffusion of the first dopant from the silicon wafer into the second epitaxial layer.

    TRENCH MOSFET CONTACTS
    2.
    发明申请
    TRENCH MOSFET CONTACTS 审中-公开

    公开(公告)号：US20200083366A1

    公开(公告)日：2020-03-12

    申请号：US16128139

    申请日：2018-09-11

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Prasad VENKATRAMAN ,  Dean E. PROBST

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

    Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. The second type of device cell includes a trench that is wider than the trench in the first device cell, but a mesa of the second type of device cell has about the same width as the mesa of the first type of device cell. Having about the same width, the mesa in the second type of device cell in the contact area has similar breakdown characteristics as a mesa in the first type of device cell in the active area of the device.

    SHIELD CONTACT LAYOUT FOR POWER MOSFETS
    3.
    发明申请
    SHIELD CONTACT LAYOUT FOR POWER MOSFETS 有权

    公开(公告)号：US20220310802A1

    公开(公告)日：2022-09-29

    申请号：US17655579

    申请日：2022-03-21

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Prasad VENKATRAMAN ,  Peter BURKE ,  Gary Horst LOECHELT ,  Balaji PADMANABHAN ,  Emily M. LINEHAN

    IPC: H01L29/40 ,  H01L29/423

    Abstract: A method includes defining a plurality of trenches of a first type that extend in a longitudinal direction in a semiconductor substrate, and defining a trench of a second type extending in a lateral direction and intersecting the plurality of trenches of the first type. The trench of the second type is in fluid communication with each of the intersected plurality of trenches of the first type. The method further includes disposing a shield poly layer in the plurality of trenches of the first type and the trench of the second type, disposing an inter-poly dielectric layer and a gate poly layer above the shield poly layer in the plurality of trenches of the first type and the trench of the second type, and forming an electrical contact to the shield poly layer through an opening in the inter-poly dielectric layer and the gate poly layer disposed in the trench of the second type.

    ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN
    5.
    发明申请
    ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN 有权
    电子设备，其中包括TRENCH和导电结构

    公开(公告)号：US20140151787A1

    公开(公告)日：2014-06-05

    申请号：US14176185

    申请日：2014-02-10

    Applicant: Semiconductor Components Industries, LLC

    Inventor： Prasad VENKATRAMAN ,  Balaji PADMANABHAN

    IPC: H01L29/78

    CPC classification number: H01L29/7827 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

    Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence.

    Abstract translation: 电子器件可以包括晶体管结构，其包括覆盖在衬底上并具有主表面的图案化半导体层，其中所述图案化半导体层限定从所述主表面朝向所述衬底延伸的第一沟槽和第二沟槽。 电子器件还可以包括在第一沟槽内的第一导电电极和栅电极。 电子器件还可以在第二沟槽内进一步包括第二导电电极。 电子器件可以包括图案化半导体层内的源极区域，并且设置在第一和第二沟槽之间。 电子器件还可以包括在图案化的半导体层内以及在第一和第二沟槽之间的体接触区域，其中主体接触区域与主表面间隔开。 形成电子器件的过程可以利用在处理序列期间形成所有沟槽的优点。

    ELECTRONIC DEVICE COMPRISING CONDUCTIVE STRUCTURES AND AN INSULATING LAYER BETWEEN THE CONDUCTIVE STRUCTURES AND WITHIN A TRENCH
    6.
    发明申请
    ELECTRONIC DEVICE COMPRISING CONDUCTIVE STRUCTURES AND AN INSULATING LAYER BETWEEN THE CONDUCTIVE STRUCTURES AND WITHIN A TRENCH 有权
    包含导电结构的电子器件和导电结构之间的绝缘层和在TRENCH中之间的绝缘层

    公开(公告)号：US20140103424A1

    公开(公告)日：2014-04-17

    申请号：US14106504

    申请日：2013-12-13

    Applicant: Semiconductor Components Industries, LLC

    Inventor： Gary H. LOECHELT ,  Prasad VENKATRAMAN

    IPC: H01L29/417 ,  H01L29/78

    CPC classification number: H01L29/41741 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L29/7816 ,  H01L29/7827 ,  H01L29/7835

    Abstract: An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow RDSON to be lower for a given BVDSS.

    Abstract translation: 电子器件可以包括包括下面的掺杂区域和覆盖衬底的半导体层的衬底。 沟槽可以具有侧壁并且至少部分地延伸穿过半导体层。 电子器件还可以包括邻近下面的掺杂区域的第一导电结构，绝缘层和沟槽内的第二导电结构。 绝缘层可以设置在第一和第二导电结构之间，并且第一导电结构可以设置在绝缘层和下面的掺杂区域之间。 可以执行形成电子器件的工艺，使得第一导电结构包括导电填充材料或半导体层内的掺杂区域。 第一导电结构可以允许下面的掺杂区域离沟道区域更远，并允许给定BVDSS的RDSON较低。

    TRENCH MOSFET CONTACTS
    9.
    发明申请
    TRENCH MOSFET CONTACTS 审中-公开

    公开(公告)号：US20200220009A1

    公开(公告)日：2020-07-09

    申请号：US16825945

    申请日：2020-03-20

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Prasad VENKATRAMAN ,  Dean E. PROBST

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

    Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each first type of device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. Each second type of device cell in the gate or shield contact area includes a trench that is wider and deeper than the trench in the first type device cell.

    CIRCUIT WITH TRANSISTORS HAVING COUPLED GATES
    10.
    发明申请
    CIRCUIT WITH TRANSISTORS HAVING COUPLED GATES 审中-公开

    公开(公告)号：US20180026630A1

    公开(公告)日：2018-01-25

    申请号：US15215310

    申请日：2016-07-20

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jaume ROIG-GUITART ,  Balaji PADMANABHAN ,  Prasad VENKATRAMAN

    IPC: H03K17/687 ,  H01L29/20 ,  H01L29/778

    CPC classification number: H03K17/165 ,  H03K2217/0036 ,  H03K2217/0054

    Abstract: A circuit can include a first transistor including a source and a gate; a second transistor including a drain and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and a switchable element. In one embodiment, a first current-carrying terminal of the switchable element is coupled to the gate of the first transistor, and a second current-carrying terminal of the switchable element is coupled to the gate of the second transistor. In another embodiment, the switchable element is coupled to the gate of the first transistor and includes a first selectable terminal of the switchable element coupled to a source of the second transistor, and a second selectable terminal of the switchable element coupled to the gate of the second transistor. In a particular embodiment, the circuit can be a cascode circuit

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