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公开(公告)号:US20240014261A1
公开(公告)日:2024-01-11
申请号:US18469780
申请日:2023-09-19
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Shengling DENG , Dean E. PROBST , Zia HOSSAIN
IPC: H01L29/06 , H01L29/78 , H01L29/739 , H01L29/868 , H01L29/66 , H01L29/08 , H01L29/10
CPC classification number: H01L29/0653 , H01L29/7804 , H01L29/7397 , H01L29/868 , H01L29/6634 , H01L29/0882 , H01L29/7813 , H01L29/66712 , H01L29/66348 , H01L29/1095
Abstract: In a general aspect, a method can include forming well region of one conductivity type in a semiconductor region of another conductivity type An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The method can further include forming at least one dielectric region in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.
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公开(公告)号:US20220085204A1
公开(公告)日:2022-03-17
申请号:US17534084
申请日:2021-11-23
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Dean E. PROBST , Peter A. BURKE , Prasad VENKATRAMAN
IPC: H01L29/78 , H01L21/765 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/739
Abstract: In one embodiment, a semiconductor device is formed having a plurality of active trenches formed within an active region of the semiconductor device. A first insulator is formed along at least a portion of sidewalls of each active trench. A perimeter termination trench is formed that surrounds the active region. The perimeter termination trench is formed having a first sidewall that is adjacent the active region and a second sidewall that is opposite the first sidewall. An insulator is formed along the second sidewall that has a thickness is greater than an insulator that is formed along the first sidewall.
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公开(公告)号:US20220407411A1
公开(公告)日:2022-12-22
申请号:US17806597
申请日:2022-06-13
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Dean E. PROBST , Joseph Andrew YEDINAK , Balaji PADMANABHAN , Peter A. BURKE , Jeffery A. NEULS , Ashok CHALLA
Abstract: In some aspects, the techniques described herein relate to a circuit including: a metal-oxide semiconductor field-effect transistor (MOSFET) including a gate, a source, and a drain; and a snubber circuit coupled between the drain and the source, the snubber circuit including: a diode having a cathode and an anode, the cathode being coupled with the drain; a capacitor having a first terminal coupled with the anode, and a second terminal coupled with the source; and a resistor having a first terminal coupled with the anode and the first terminal of the capacitor, and a second terminal coupled with the source.
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公开(公告)号:US20210391422A1
公开(公告)日:2021-12-16
申请号:US17446238
申请日:2021-08-27
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Shengling DENG , Dean E. PROBST , Zia HOSSAIN
IPC: H01L29/06 , H01L29/78 , H01L29/739 , H01L29/868 , H01L29/66 , H01L29/08 , H01L29/10
Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.
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公开(公告)号:US20200083366A1
公开(公告)日:2020-03-12
申请号:US16128139
申请日:2018-09-11
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Prasad VENKATRAMAN , Dean E. PROBST
IPC: H01L29/78 , H01L29/417 , H01L29/66
Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. The second type of device cell includes a trench that is wider than the trench in the first device cell, but a mesa of the second type of device cell has about the same width as the mesa of the first type of device cell. Having about the same width, the mesa in the second type of device cell in the contact area has similar breakdown characteristics as a mesa in the first type of device cell in the active area of the device.
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公开(公告)号:US20190326392A1
公开(公告)日:2019-10-24
申请号:US15959479
申请日:2018-04-23
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Shengling DENG , Dean E. PROBST , Zia HOSSAIN
IPC: H01L29/06 , H01L29/78 , H01L29/739 , H01L29/868 , H01L29/10 , H01L29/08 , H01L29/66
Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.
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公开(公告)号:US20230403003A1
公开(公告)日:2023-12-14
申请号:US18310153
申请日:2023-05-01
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Jaume ROIG-GUITART , Dean E. PROBST , Ashok Challa
IPC: H03K17/16 , H03K17/0412 , H01L29/78 , H01L27/088 , H01L27/06
CPC classification number: H03K17/161 , H03K17/04123 , H01L29/7813 , H01L27/088 , H01L27/0629
Abstract: A circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) and a snubber circuit coupled between a drain and a source of the MOSFET. The snubber circuit includes a transistor disposed in parallel to the MOSFET. The transistor has a floating gate. The circuit further includes a capacitor in series with the transistor, and a resistor disposed parallel to the capacitor.
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公开(公告)号:US20210111106A1
公开(公告)日:2021-04-15
申请号:US16675525
申请日:2019-11-06
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Jeffrey Peter GAMBINO , David T. Price , Jeffery A. NEULS , Dean E. PROBST , Santosh MENON , Peter A. BURKE , Bigildis DOSDOS
IPC: H01L23/495 , H01L23/00 , H01L25/11 , H01L25/00
Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.
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公开(公告)号:US20250096679A1
公开(公告)日:2025-03-20
申请号:US18468400
申请日:2023-09-15
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Jaume ROIG-GUITART , Dean E. PROBST
IPC: H02M3/158 , H03K17/687
Abstract: In a general aspect, a circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a source, and a drain. The MOSFET has a first breakdown voltage. The circuit also includes a clamping circuit coupled between the drain and the source. The clamping circuit including a diode having a second breakdown voltage that is less than the first breakdown voltage. A cathode of the diode is coupled with the drain of the MOSFET. The clamping circuit further includes an inductor having a first terminal coupled with an anode of the diode, and a second terminal coupled with the source of the MOSFET.
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公开(公告)号:US20230352577A1
公开(公告)日:2023-11-02
申请号:US18171029
申请日:2023-02-17
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Peter MOENS , Balaji PADMANABHAN , Dean E. PROBST , Prasad VENKATRAMAN , Tirthajyoti SARKAR , Gary Horst LOECHELT
CPC classification number: H01L29/7813 , H01L29/0696 , H01L29/407 , H01L29/66734
Abstract: An accumulation MOSFET includes a plurality of device cells. Each device cell includes a mesa adjoining a vertical trench is disposed in a doped semiconductor substrate. The mesa has a top mesa portion disposed on a bottom mesa portion. The top mesa portion has a width that is narrower than a width of the bottom mesa portion. The vertical trench adjoining the mesa has a top trench portion and a bottom trench portion. The top trench portion has a width that is wider than a width of the bottom trench portion. A dielectric is disposed on a sidewall of the vertical trench. A gate electrode disposed in the top trench portion forms an accumulation channel region in the top mesa portion and a shield electrode disposed in the bottom trench portion forms a depletion drift region in the bottom mesa portion.
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