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公开(公告)号:US20240215291A1
公开(公告)日:2024-06-27
申请号:US18555927
申请日:2022-04-11
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Shinya SASAGAWA , Ryota HODO , Hiroaki HONDA , Yasunori SASAMURA
IPC: H10K50/13 , H10K59/131 , H10K71/00 , H10K71/40 , H10K71/60
CPC classification number: H10K50/13 , H10K59/131 , H10K71/40 , H10K71/60 , H10K71/621
Abstract: Provided is a display device with high display quality. The display device includes a first pixel and a second pixel provided to be adjacent to the first pixel. The first pixel includes a first pixel electrode, a first EL layer over the first pixel electrode, and a common electrode over the first EL layer; the second pixel includes a second pixel electrode, a second EL layer over the second pixel electrode, and the common electrode over the second EL layer; each of the first pixel electrode and the second pixel electrode has a tapered shape on a side surface; a taper angle of the tapered shape is smaller than 90 degrees; and the display device includes a region where the distance between the first pixel electrode and the second pixel electrode is less than or equal to one micrometer.
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公开(公告)号:US20220199832A1
公开(公告)日:2022-06-23
申请号:US17606823
申请日:2020-05-12
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Shunpei YAMAZAKI , Ryota HODO , Katsuaki TOCHIBAYASHI , Hiroaki HONDA , Kentaro SUGAYA
IPC: H01L29/786
Abstract: A semiconductor device with small variations in transistor characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor provided apart from each other over the oxide; an insulator in a region between the first conductor and the second conductor over the oxide; and a conductor over the insulator. A side surface of the oxide, a top surface of the first conductor, a side surface of the first conductor, a top surface of the second conductor, and a side surface of the second conductor include regions in contact with a nitride containing silicon.
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公开(公告)号:US20210242345A1
公开(公告)日:2021-08-05
申请号:US17049042
申请日:2019-05-14
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Shunpei YAMAZAKI , Erika TAKAHASHI , Hiroaki HONDA , Kentaro SUGAYA , Shinya SASAGAWA
IPC: H01L29/786 , H01L29/04 , H01L29/24 , H01L21/02 , H01L29/66
Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first oxide, a second oxide, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor is provided in contact with a top surface of the first oxide. The second conductor is provided in contact with the top surface of the first oxide. The first insulator is provided over the first conductor and the second conductor. The second oxide is provided in contact with the top surface of the first oxide. The second insulator is provided over the second oxide. The third conductor is provided over the second insulator. The first insulator has a function of inhibiting diffusion of oxygen. The first oxide includes indium, an element M (M is gallium, yttrium, or tin), and zinc. The first oxide includes a first region overlapping with the third conductor. A region of the first region in contact with the second oxide includes a region in which an atomic ratio of aluminum (Al) to the element M is less than 0.1.
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公开(公告)号:US20180286886A1
公开(公告)日:2018-10-04
申请号:US15925122
申请日:2018-03-19
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Hajime KIMURA , Tsutomu MURAKAWA , Kosei NEI , Hiroaki HONDA , Yusuke SHINO
IPC: H01L27/12 , G11C11/404 , H01L29/786 , H01L27/06 , H01L21/84
Abstract: A semiconductor device which can suppress leakage current between a wiring and a connection electrode connected to a floating node is provided. The semiconductor device includes a first insulator, a first conductor over the first insulator, a second conductor over the first insulator, and a second insulator over the first insulator, the first conductor, and the second conductor. The first conductor and the second conductor contain a metal A (one kind or a plurality of kinds of aluminum, copper, tungsten, chromium, silver, gold, platinum, tantalum, nickel, molybdenum, magnesium, beryllium, indium, and ruthenium). The metal A is detected in an interface between the first insulator and the second insulator by an energy dispersive X-ray spectroscopy (EDX). The second insulator includes a groove for exposing the first insulator between the first conductor and the second conductor.
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公开(公告)号:US20200185528A1
公开(公告)日:2020-06-11
申请号:US16634493
申请日:2018-07-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Shunpei YAMAZAKI , Daisuke MATSUBAYASHI , Ryota HODO , Daigo ITO , Hiroaki HONDA , Satoru OKAMOTO
IPC: H01L29/786 , G11C11/4091 , H01L27/108 , H01L27/105 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/24
Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor over the oxide; a third conductor over the oxide; a first insulator provided between the oxide and the third conductor and covering a side surface of the third conductor; a second insulator over the third conductor and the first insulator; a third insulator positioned over the first conductor and at a side surface of the second insulator; a fourth insulator positioned over the second conductor and at a side surface of the second insulator; a fourth conductor being in contact with a top surface and a side surface of the third insulator and electrically connected to the first conductor; and a fifth conductor being in contact with a top surface and a side surface of the fourth insulator and electrically connected to the second conductor. The first insulator is between the third insulator and the third conductor, and between the fourth insulator and the third conductor.
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公开(公告)号:US20180108647A1
公开(公告)日:2018-04-19
申请号:US15725519
申请日:2017-10-05
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Naoki OKUNO , Kosei NEI , Hiroaki HONDA , Naoto YAMADE , Hiroshi FUJIKI
IPC: H01L27/02 , H01L27/11519 , H01L27/11565 , H01L29/786
CPC classification number: H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L29/78609 , H01L29/78618 , H01L29/78648 , H01L29/7869 , H01L29/78693 , H01L29/78696
Abstract: A transistor includes a first insulator over a substrate; a first oxide thereover; a second oxide in contact with at least part of the top surface of the first oxide; a first conductor and a second conductor each in contact with at least part of the top surface of the second oxide; a third oxide that is over the first conductor and the second conductor and is in contact with at least part of the top surface of the second oxide; a second insulator thereover; a third conductor which is over the second insulator and at least part of which overlaps with a region between the first conductor and the second conductor; and a third insulator which is over the third conductor and at least part of which is in contact with the top surface of the first insulator. The thickness of a region of the first insulator that is in contact with the third insulator is less than the thickness of a region of the first insulator that is in contact with the first oxide.
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7.
公开(公告)号:US20160293766A1
公开(公告)日:2016-10-06
申请号:US15175183
申请日:2016-06-07
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Motomu KURATA , Shinya SASAGAWA , Taiga MURAOKA , Hiroaki HONDA , Takashi HAMADA
IPC: H01L29/786 , H01L29/417
CPC classification number: H01L29/7869 , H01L21/02334 , H01L27/1225 , H01L29/41733 , H01L29/66969 , H01L29/78696
Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.
Abstract translation: 准备具有绝缘表面的基板; 在基板上形成包括第一氧化物半导体层和第二氧化物半导体层的层叠膜; 在层叠膜的一部分上形成掩模层,然后进行干法蚀刻处理,从而除去保留有掩模层的区域,在其余的侧面形成反应产物 叠片 去除掩模层后,通过湿蚀刻处理去除反应产物; 源极电极和漏电极形成在堆叠膜上; 并且第三氧化物半导体层,栅极绝缘膜和栅极电极按顺序层叠并形成在堆叠膜上,以及源电极和漏电极。
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公开(公告)号:US20200006319A1
公开(公告)日:2020-01-02
申请号:US16561501
申请日:2019-09-05
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Naoki OKUNO , Kosei NEI , Hiroaki HONDA , Naoto YAMADE , Hiroshi FUJIKI
IPC: H01L27/02 , H01L27/11521 , H01L27/11519 , H01L27/11565 , H01L29/786
Abstract: A transistor includes a first insulator over a substrate; a first oxide thereover; a second oxide in contact with at least part of the top surface of the first oxide; a first conductor and a second conductor each in contact with at least part of the top surface of the second oxide; a third oxide that is over the first conductor and the second conductor and is in contact with at least part of the top surface of the second oxide; a second insulator thereover; a third conductor which is over the second insulator and at least part of which overlaps with a region between the first conductor and the second conductor; and a third insulator which is over the third conductor and at least part of which is in contact with the top surface of the first insulator. The thickness of a region of the first insulator that is in contact with the third insulator is less than the thickness of a region of the first insulator that is in contact with the first oxide.
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9.
公开(公告)号:US20160233340A1
公开(公告)日:2016-08-11
申请号:US15017831
申请日:2016-02-08
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Akihisa SHIMOMURA , Satoru OKAMOTO , Yutaka OKAZAKI , Yoshinobu ASAMI , Hiroaki HONDA , Takuya TSURUME
IPC: H01L29/786 , H01L29/06 , H01L29/423
CPC classification number: H01L29/7869 , H01L21/385 , H01L27/1225 , H01L29/0688 , H01L29/42384 , H01L29/78696
Abstract: A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A semiconductor device having a high degree of integration is provided. Side surfaces of an oxide semiconductor layer in which a channel is formed are covered with an oxide semiconductor layer, whereby impurity diffusion from the side surfaces of the oxide semiconductor into the inside can be prevented. A gate electrode is formed by a damascene process, whereby transistors can be miniaturized and formed at a high density.
Abstract translation: 提供具有良好电特性的晶体管。 提供具有稳定电特性的晶体管。 提供了具有高集成度的半导体器件。 其中沟道形成的氧化物半导体层的侧表面被氧化物半导体层覆盖,从而可以防止从氧化物半导体的侧表面向内部的杂质扩散。 栅电极通过镶嵌工艺形成,由此可以以高密度小型化和形成晶体管。
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10.
公开(公告)号:US20140291674A1
公开(公告)日:2014-10-02
申请号:US14227459
申请日:2014-03-27
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Motomu KURATA , Shinya SASAGAWA , Taiga MURAOKA , Hiroaki HONDA , Takashi HAMADA
IPC: H01L29/786 , H01L27/12 , H01L29/66
CPC classification number: H01L29/7869 , H01L21/02334 , H01L27/1225 , H01L29/41733 , H01L29/66969 , H01L29/78696
Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.
Abstract translation: 准备具有绝缘表面的基板; 在基板上形成包括第一氧化物半导体层和第二氧化物半导体层的层叠膜; 在层叠膜的一部分上形成掩模层,然后进行干法蚀刻处理,从而除去保留有掩模层的区域,在其余的侧面形成反应产物 叠片 去除掩模层后,通过湿蚀刻处理去除反应产物; 源极电极和漏电极形成在堆叠膜上; 并且第三氧化物半导体层,栅极绝缘膜和栅极电极按顺序层叠并形成在堆叠膜上,以及源电极和漏电极。
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