公开(公告)号：US20240395825A1

公开(公告)日：2024-11-28

申请号：US18789755

申请日：2024-07-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  G11C7/04 ,  H01L29/04 ,  H01L29/78 ,  H01L29/786 ,  H03K19/00 ,  H03K19/0185

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US20170062044A1

公开(公告)日：2017-03-02

申请号：US15260400

申请日：2016-09-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Wataru UESUGI ,  Kiyoshi KATO ,  Tatsuya ONUKI

IPC: G11C11/419 ,  H01L21/02 ,  H01L29/786 ,  H01L27/11 ,  G11C11/418 ,  H01L27/12

CPC classification number: G11C11/419 ,  G06F2212/221 ,  G11C5/14 ,  G11C5/148 ,  G11C11/418 ,  G11C14/0054 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.

Abstract translation: 提供具有新颖结构的半导体器件。 提供一种降低功耗的半导体器件。 包括能够将数据备份到非易失性存储器的SRAM和存储器单元的外围电路的存储单元被配置为提供不同的功率门控状态。 在非常短的第一时段中，通过关闭开关使位线进入电浮动状态。 在比第一期间长的第二期间，对存储单元进行电力门控。 在比第二时段长的第三时段中，对存储单元和外围电路进行功率门控。

公开(公告)号：US20220328530A1

公开(公告)日：2022-10-13

申请号：US17845112

申请日：2022-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  H01L29/786 ,  H01L49/02 ,  H01L29/04 ,  H01L29/78 ,  H03K19/00 ,  H03K19/0185 ,  G11C7/04

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US20170373092A1

公开(公告)日：2017-12-28

申请号：US15644916

申请日：2017-07-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  H03K19/00 ,  H01L49/02 ,  H01L29/78 ,  G11C7/04 ,  H01L29/04 ,  H03K19/0185 ,  H01L29/786

CPC classification number: H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US20170005658A1

公开(公告)日：2017-01-05

申请号：US15199004

申请日：2016-06-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H03K19/00 ,  H03K3/037 ,  H01L29/04 ,  H01L27/108 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

Abstract translation: 逻辑电路中提供的保持电路使能电源门控。 保持电路包括第一端子，节点，电容器以及第一至第三晶体管。 第一晶体管控制逻辑电路的第一端子和输入端子之间的电连接。 第二晶体管控制逻辑电路的输出端和节点之间的电连接。 第三晶体管控制节点与逻辑电路的输入端之间的电连接。 第一晶体管的栅极电连接到第二晶体管的栅极。 在数据保留期间，节点变为电浮动。 节点的电压由电容器保持。

公开(公告)号：US20160351552A1

公开(公告)日：2016-12-01

申请号：US15161575

申请日：2016-05-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kei TAKAHASHI ,  Wataru UESUGI ,  Hiromichi GODO

IPC: H01L25/18 ,  G06F3/041 ,  G06F3/044 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1335 ,  G02F1/1339 ,  G02F1/1341 ,  H01L27/32 ,  G06F3/047

CPC classification number: G06F3/047 ,  G02F1/13338 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/0418 ,  G06F3/044 ,  G06F2203/04102 ,  G06F2203/04103 ,  H01L27/323 ,  H01L2224/4847

Abstract: To provide a display device which includes a touch sensor and a large number of pixels and in which a driver circuit of a display portion and a driver circuit of a touch sensor are formed in one IC. The display device includes the display portion, the touch sensor, and a plurality of ICs. The plurality of ICs each include a first circuit. One of the plurality of ICs includes a second circuit and a third circuit. The first circuit has a function of outputting a video signal to the display portion. The second circuit has a function of outputting a signal for driving a sensor element included in the touch sensor. The third circuit has a function of converting an analog signal output from the sensor element into a digital signal.

Abstract translation: 提供一种包括触摸传感器和大量像素的显示装置，其中在一个IC中形成显示部分的驱动电路和触摸传感器的驱动电路。 显示装置包括显示部分，触摸传感器和多个IC。 多个IC各自包括第一电路。 多个IC中的一个包括第二电路和第三电路。 第一电路具有将视频信号输出到显示部分的功能。 第二电路具有输出用于驱动包括在触摸传感器中的传感器元件的信号的功能。 第三电路具有将从传感器元件输出的模拟信号转换为数字信号的功能。

公开(公告)号：US20160233866A1

公开(公告)日：2016-08-11

申请号：US15017879

申请日：2016-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Wataru UESUGI

IPC: H03K19/0175 ,  H03K19/00 ,  G11C5/14 ,  G11C11/413

CPC classification number: H03K19/017509 ,  G11C8/08 ,  G11C11/4125 ,  G11C29/50016 ,  G11C2029/5002 ,  H03K19/0008

Abstract: A semiconductor device with lower power consumption and an electronic device including the same are provided. To reduce leakage current flowing in a word line driver circuit, a switching element is provided, specifically, between the word line driver circuit and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the word line driver circuit. Furthermore, to reduce the stand-by power due to precharge of a bit line, a switching element is provided in a bit line driver circuit, specifically, between the bit line and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the bit line driver circuit.

Abstract translation: 提供具有较低功耗的半导体器件和包括该半导体器件的电子器件。 为了减少在字线驱动电路中流动的泄漏电流，特别地，在字线驱动电路和高电压或低电压电源之间提供开关元件。 当没有存储器访问时，开关元件被关闭，从而中断从高电压或低电压电源到字线驱动电路的电压（或电流）的施加。 此外，为了减少由于位线的预充电引起的待机功率，开关元件设置在位线驱动电路中，具体地，位于位线和高电压或低电压电源之间。 当没有存储器访问时，开关元件被关断，从而中断从高电压或低电压电源施加到位线驱动电路的电压（或电流）。

公开(公告)号：US20160105174A1

公开(公告)日：2016-04-14

申请号：US14874607

申请日：2015-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H03K19/00 ,  H01L49/02 ,  H01L29/04 ,  H01L27/12 ,  H03K19/0185 ,  H01L29/78

CPC classification number: H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

Abstract translation: 逻辑电路中提供的保持电路使能电源门控。 保持电路包括第一端子，节点，电容器以及第一至第三晶体管。 第一晶体管控制逻辑电路的第一端子和输入端子之间的电连接。 第二晶体管控制逻辑电路的输出端和节点之间的电连接。 第三晶体管控制节点与逻辑电路的输入端之间的电连接。 第一晶体管的栅极电连接到第二晶体管的栅极。 在数据保留期间，节点变为电浮动。 节点的电压由电容器保持。

公开(公告)号：US20210074734A1

公开(公告)日：2021-03-11

申请号：US17083393

申请日：2020-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  H01L29/786 ,  H01L49/02 ,  H01L29/04 ,  H01L29/78 ,  H03K19/00 ,  H03K19/0185 ,  G11C7/04

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US20200168635A1

公开(公告)日：2020-05-28

申请号：US16657277

申请日：2019-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  H01L29/04 ,  G11C7/04 ,  H03K19/0185 ,  H03K19/00 ,  H01L29/78 ,  H01L49/02 ,  H01L29/786

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.