公开(公告)号：US11764128B2

公开(公告)日：2023-09-19

申请号：US17322557

申请日：2021-05-17

申请人： SK hynix Inc.

发明人： Seung Hwan Kim ,  Hyun Chul Seo ,  Hyeong Seok Choi ,  Moon Un Hyun

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/14335

摘要： A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

公开(公告)号：US09070691B2

公开(公告)日：2015-06-30

申请号：US14341288

申请日：2014-07-25

申请人： SK HYNIX INC.

发明人： Jae Sung Oh ,  Moon Un Hyun ,  Jong Hyun Kim ,  Jin Ho Gwon

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/04 ,  H01L29/40 ,  H01L23/538 ,  H01L21/48 ,  H01L21/673 ,  H01L23/32 ,  H01L25/10 ,  H01L25/11 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/5386 ,  H01L21/486 ,  H01L21/67346 ,  H01L23/3128 ,  H01L23/32 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/08111 ,  H01L2224/16225 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/32146 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01087

摘要： A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A to semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

摘要翻译： 半导体封装包括具有第一区域的基板主体的基板，围绕第一区域限定的第二区域和围绕第二区域限定的第三区域。 布线被放置在基板主体上，并且布线具有延伸到第三区域的第一端。 连接图案被放置在第三区域中并且电连接到布线的第一端。 A至半导体芯片设置在第一区域中并与各布线电连接，并且模制构件设置在第一和第二区域中并且覆盖半导体芯片。

公开(公告)号：US08823158B2

公开(公告)日：2014-09-02

申请号：US13630239

申请日：2012-09-28

申请人： SK Hynix Inc.

发明人： Jae Sung Oh ,  Moon Un Hyun ,  Jong Hyun Kim ,  Jin Ho Gwon ,  Dong You Kim ,  Ki Bon Cha

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5386 ,  H01L21/486 ,  H01L21/67346 ,  H01L23/3128 ,  H01L23/32 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/08111 ,  H01L2224/16225 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/32146 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01087

摘要： A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

摘要翻译： 半导体封装包括具有第一区域的基板主体的基板，围绕第一区域限定的第二区域和围绕第二区域限定的第三区域。 布线被放置在基板主体上，并且布线具有延伸到第三区域的第一端。 连接图案被放置在第三区域中并且电连接到布线的第一端。 半导体芯片设置在第一区域中并且电连接到各个布线，并且模制构件设置在第一和第二区域中并且覆盖半导体芯片。