公开(公告)号：US20160131697A1

公开(公告)日：2016-05-12

申请号：US14537608

申请日：2014-11-10

Applicant: SK hynix Inc.

Inventor： Tae Jin KANG

IPC: G01R31/26 ,  G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/225 ,  G11C29/06 ,  G11C29/12005

Abstract: A semiconductor apparatus includes a clock buffer and a reference voltage generation unit. The clock buffer generates an internal clock signal, based on first and second clock signals, in a first operation mode, and generates the internal clock signal, based on the first clock signal and a reference voltage, when a normal operation test is performed in a second operation mode. The reference voltage generation unit generates the reference voltage when the normal operation test is performed in the second operation mode.

Abstract translation: 半导体装置包括时钟缓冲器和参考电压产生单元。 时钟缓冲器在第一操作模式中基于第一和第二时钟信号产生内部时钟信号，并且当在第一操作模式中执行正常操作测试时，基于第一时钟信号和参考电压产生内部时钟信号 第二操作模式。 当在第二操作模式下执行正常操作测试时，参考电压产生单元产生参考电压。

公开(公告)号：US20150338456A1

公开(公告)日：2015-11-26

申请号：US14816591

申请日：2015-08-03

Applicant: SK hynix Inc.

Inventor： Young Suk SEO ,  Ho Uk SONG ,  Jun Hyun CHUN ,  Tae Jin KANG

IPC: G01R31/26 ,  H03L7/06 ,  H03L1/00

CPC classification number: G01R31/2644 ,  G01R31/2607 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/50012 ,  H03L1/00 ,  H03L7/06

Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.

Abstract translation: 一种半导体装置，包括：输出定时控制器，被配置为将施加的外部读取命令延迟预定时间，并且在正常模式期间产生正常输出使能标志信号，所述测试输出定时控制器被配置为从外部产生DLL时钟信号 时钟信号，与DLL时钟信号同步地延迟施加的外部读取命令，并且在测试模式期间输出延迟的外部应用外部读取命令作为测试输出使能标志信号，以及多路复用器（MUX），其被配置为输出任何一个 正常输出使能标志信号或测试输出使能标志信号作为输出使能标志信号。

公开(公告)号：US20150221359A1

公开(公告)日：2015-08-06

申请号：US14174647

申请日：2014-02-06

Applicant: SK hynix Inc.

Inventor： Tae Jin KANG

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C11/4087 ,  G11C29/12015 ,  G11C29/46

Abstract: A semiconductor device includes a section signal generator and a decoder. The section signal generator generates a section signal by retarding a pre-section signal including a pulse created during a read operation or a write operation by a delay time that is set according to a level combination of first and second test mode signals. The decoder decodes address signals in response to a pulse of the section signal to generate column selection signals, one of which is selectively enabled, to store an external data in a memory cell of an internal circuit or to output a data stored in a memory cell of an internal circuit.

Abstract translation: 半导体器件包括部分信号发生器和解码器。 区段信号发生器通过将包括在读取操作或写入操作期间产生的脉冲的预分段信号延迟根据第一和第二测试模式信号的电平组合设置的延迟时间来产生分段信号。 解码器响应于区段信号的脉冲对地址信号进行解码，以产生列选择信号，其中一个被选择性地使能，以将外部数据存储在内部电路的存储单元中，或者输出存储在存储单元中的数据 的内部电路。

公开(公告)号：US20150016196A1

公开(公告)日：2015-01-15

申请号：US14489575

申请日：2014-09-18

Applicant: SK hynix Inc.

Inventor： Kyoung Hwan KWON ,  Tae Jin KANG ,  Sang Kwon LEE

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222

Abstract: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.

Abstract translation: 数据输入电路包括时钟采样单元，最终时钟产生单元和写入锁存信号产生单元。 采样单元被配置为产生包括在写入等待时间之后产生的脉冲的移位信号，并且在从产生移位信号的脉冲的时间开始的脉冲串周期期间，通过对内部时钟进行采样来产生采样时钟。 最终时钟生成单元被配置为通过与采样时钟同步地锁存移位信号来产生电平信号，并且响应于突发信号从电平信号产生最终时钟。 写锁存信号生成单元被配置为通过锁存最终时钟来产生使能信号，并且响应于使能信号产生用于锁存和输出对准数据的写锁存信号。

公开(公告)号：US20140176167A1

公开(公告)日：2014-06-26

申请号：US13845308

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Young Suk SEO ,  Ho Uk SONG ,  Jun Hyun CHUN ,  Tae Jin KANG

IPC: G01R31/26

CPC classification number: G01R31/2644 ,  G01R31/2607 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/50012 ,  H03L1/00 ,  H03L7/06

Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.

Abstract translation: 一种半导体装置，包括：输出定时控制器，被配置为将施加的外部读取命令延迟预定时间，并且在正常模式期间产生正常输出使能标志信号，所述测试输出定时控制器被配置为从外部产生DLL时钟信号 时钟信号，与DLL时钟信号同步地延迟施加的外部读取命令，并且在测试模式期间输出延迟的外部应用外部读取命令作为测试输出使能标志信号，以及多路复用器（MUX），其被配置为输出任何一个 正常输出使能标志信号或测试输出使能标志信号作为输出使能标志信号。