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    SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME 有权
    半导体器件和半导体系统，包括它们

    公开(公告)号：US20140368261A1

    公开(公告)日：2014-12-18

    申请号：US14156904

    申请日：2014-01-16

    Applicant: SK hynix Inc.

    Inventor： Sun Young HWANG ,  Jun Hyun CHUN

    IPC: H01H85/04

    CPC classification number: G11C17/18 ,  G11C5/148

    Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.

    Abstract translation: 提供半导体系统。 半导体系统包括控制器和半导体器件。 控制器产生电源电压信号。 半导体器件响应于电源电压信号产生上电信号，产生第一选择脉冲，第二选择脉冲和初始化脉冲信号，产生用于根据切换状态控制内部操作的第一熔丝信号 并且产生用于根据第二保险丝的切断状态控制内部操作的第二熔丝信号。

    SEMICONDUCTOR APPARATUS
    3.
    发明申请
    SEMICONDUCTOR APPARATUS 有权

    公开(公告)号：US20140176167A1

    公开(公告)日：2014-06-26

    申请号：US13845308

    申请日：2013-03-18

    Applicant: SK HYNIX INC.

    Inventor： Young Suk SEO ,  Ho Uk SONG ,  Jun Hyun CHUN ,  Tae Jin KANG

    IPC: G01R31/26

    CPC classification number: G01R31/2644 ,  G01R31/2607 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/50012 ,  H03L1/00 ,  H03L7/06

    Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.

    Abstract translation: 一种半导体装置，包括：输出定时控制器，被配置为将施加的外部读取命令延迟预定时间，并且在正常模式期间产生正常输出使能标志信号，所述测试输出定时控制器被配置为从外部产生DLL时钟信号 时钟信号，与DLL时钟信号同步地延迟施加的外部读取命令，并且在测试模式期间输出延迟的外部应用外部读取命令作为测试输出使能标志信号，以及多路复用器（MUX），其被配置为输出任何一个 正常输出使能标志信号或测试输出使能标志信号作为输出使能标志信号。

    CONTROLLER AND MEMORY SYSTEM HAVING THE SAME
    6.
    发明申请
    CONTROLLER AND MEMORY SYSTEM HAVING THE SAME 有权

    公开(公告)号：US20220165329A1

    公开(公告)日：2022-05-26

    申请号：US17340922

    申请日：2021-06-07

    Applicant: SK hynix Inc.

    Inventor： Hyun Ju YOON ,  Min KANG ,  Dong Uc KO ,  Dong Keun KIM ,  Young Su OH ,  Jun Hyun CHUN

    IPC: G11C11/406

    Abstract: A memory system is provided to include a storage device including memory cells for storing data, and a controller in communication with an external device and configured to control the storage device based on a request from the external device. The controller is configured to receive a request from the external device to perform a refresh operation of re-writing stored data in the memory cells, read data from the memory cells included in the storage device, set a refresh period based on a number of fail bits included in the read data and a temperature of the controller or the storage device, and perform the refresh operation of the storage device based on the refresh period.

    SEMICONDUCTOR APPARATUS
    7.
    发明申请
    SEMICONDUCTOR APPARATUS 有权

    公开(公告)号：US20150338456A1

    公开(公告)日：2015-11-26

    申请号：US14816591

    申请日：2015-08-03

    Applicant: SK hynix Inc.

    Inventor： Young Suk SEO ,  Ho Uk SONG ,  Jun Hyun CHUN ,  Tae Jin KANG

    IPC: G01R31/26 ,  H03L7/06 ,  H03L1/00

    CPC classification number: G01R31/2644 ,  G01R31/2607 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/50012 ,  H03L1/00 ,  H03L7/06

    Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.

    Abstract translation: 一种半导体装置，包括：输出定时控制器，被配置为将施加的外部读取命令延迟预定时间，并且在正常模式期间产生正常输出使能标志信号，所述测试输出定时控制器被配置为从外部产生DLL时钟信号 时钟信号，与DLL时钟信号同步地延迟施加的外部读取命令，并且在测试模式期间输出延迟的外部应用外部读取命令作为测试输出使能标志信号，以及多路复用器（MUX），其被配置为输出任何一个 正常输出使能标志信号或测试输出使能标志信号作为输出使能标志信号。

    MEMORY MODULE INCLUDING MODULE SUBSTRATE
    9.
    发明申请
    MEMORY MODULE INCLUDING MODULE SUBSTRATE 有权

    公开(公告)号：US20230011582A1

    公开(公告)日：2023-01-12

    申请号：US17859351

    申请日：2022-07-07

    Applicant: SK hynix Inc.

    Inventor： Dong Keun KIM ,  Min KANG ,  Dong Uc KO ,  Young Su OH ,  Hyun Ju YOON ,  Jun Hyun CHUN

    IPC: G11C11/4074 ,  G11C11/4099 ,  G11C5/14

    Abstract: A memory module includes a module substrate, a plurality of memory devices, a first power line, and a second power line. The memory devices are mounted on the module substrate. Each of the memory devices includes a power management member. The first power line may be arranged in the module substrate to provide each of the memory devices with power. The second power line may be electrically connected between the power management members of adjacent memory devices to control and share the power provided to the adjacent memory devices.

    VOLATILE MEMORY DEVICE, STORAGE DEVICE, AND OPERATING METHOD OF VOLATILE MEMORY DEVICE
    10.
    发明申请
    VOLATILE MEMORY DEVICE, STORAGE DEVICE, AND OPERATING METHOD OF VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20220165325A1

    公开(公告)日：2022-05-26

    申请号：US17337231

    申请日：2021-06-02

    Applicant: SK hynix Inc.

    Inventor： Hyun Ju YOON ,  Min KANG ,  Dong Uc KO ,  Dong Keun KIM ,  Young Su OH ,  Jun Hyun CHUN

    IPC: G11C11/408 ,  G11C11/4094

    Abstract: There are provided a volatile memory device, and an operating method. The volatile memory device includes: a plurality of memory cells arranged in rows and columns and structured to store data; word lines; bit lines; a row decoder; a column decoder; and a control logic coupled to communicate with the row and column decoders and configured to, in an active period, provide the row decoder with a first command, and provide the column decoder with a second command, wherein the row decoder is further configured to: apply a first word line voltage higher than a ground voltage to a selected word line, from when the first command is provided; and for a duration over which the row decoder is activated, apply either a second word line voltage lower than the first word line voltage to the selected word line or no voltage to the selected word line.

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