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1.发明申请公开(公告)号：US20170054436A1
公开(公告)日：2017-02-23
申请号：US14878922
申请日：2015-10-08
Applicant: SK hynix Inc.
Inventor： Myeong Jae PARK , Kyung Hoon KIM , Woo Yeol SHIN , Han Kyu CHI
CPC classification number: H03K3/0315 , H03K3/014 , H03K5/13 , H03K5/19
Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.
Abstract translation: 半导体系统可以包括被配置为输出命令和接收数据的第一半导体器件。 半导体系统可以包括：第二半导体器件，被配置为产生周期信号，响应于该命令周期性地切换的周期信号，响应周期信号输出数据，并且如果周期信号是 在预定部分期间不切换。
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公开(公告)号：US20190333553A1
公开(公告)日：2019-10-31
申请号：US16210506
申请日：2018-12-05
Applicant: SK hynix Inc.
Inventor： Geun Ho CHOI , Han Kyu CHI , Min Su PARK
Abstract: A semiconductor device includes a control circuit configured to generate a data reset signal which is enabled in response to a reset signal and first and second transfer control signals which are sequentially enabled in synchronization with a divided clock in response to a read signal and a trigger circuit configured to drive a driving signal depending on a logic level of latch data in synchronization with delayed clocks in response to the first and second transfer control signals, the driving signal having a fixed logic level based on the data reset signal being enabled.
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Patent Agency Ranking
公开(公告)号：US20170294899A1
公开(公告)日：2017-10-12
申请号：US15634646
申请日：2017-06-27
Applicant: SK hynix Inc.
Inventor： Myeong Jae PARK , Kyung Hoon KIM , Woo Yeol SHIN , Han Kyu CHI
CPC classification number: H03K3/0315 , H03K3/014 , H03K5/13 , H03K5/19
Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.
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公开(公告)号：US20180262372A1
公开(公告)日：2018-09-13
申请号：US15802922
申请日：2017-11-03
Applicant: SK hynix Inc.
Inventor： Jun Yong SONG , Jeong Kyoum KIM , Hyung Soo KIM , Han Kyu CHI
CPC classification number: H04L25/0328 , H04B1/109 , H04B1/126 , H04B1/7097 , H04B7/0862 , H04W72/082 , Y02D70/00 , Y02D70/40
Abstract: A symbol interference cancellation circuit may be provided. The symbol interference cancellation circuit may include an interference cancellation circuit configured for generating an interference-cancelled signal based on weight application signals, sampling output signals, and a clock signal.
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5.发明申请公开(公告)号：US20180183630A1
公开(公告)日：2018-06-28
申请号：US15642566
申请日：2017-07-06
Applicant: SK hynix Inc.
Inventor： Jeong Kyoum KIM , Jun Yong SONG , Han Kyu CHI
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03885
Abstract: A receiving circuit may include a decision feedback equalizer circuit and buffer. The buffer may be configured to receive an external signal and to generate an input signal. The decision feedback equalizer circuit may include a plurality of delay circuits, and may be configured to generate an internal signal based on the input signal, a strobe signal, and outputs of the plurality of delay circuits. The plurality of delay circuits may be reset based on whether or not the strobe signal has toggled or not between command signals.
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公开(公告)号：US20180183474A1
公开(公告)日：2018-06-28
申请号：US15700760
申请日：2017-09-11
Applicant: SK hynix Inc.
Inventor： Jun Yong SONG , Jeong Kyoum KIM , Hyung Soo KIM , Han Kyu CHI
IPC: H04B1/10
CPC classification number: H04B1/1036
Abstract: A symbol interference cancellation circuit may include a CTLE (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing shifted signals to the interference cancellation circuit.
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公开(公告)号：US20170237442A1
公开(公告)日：2017-08-17
申请号：US15190495
申请日：2016-06-23
Applicant: SK hynix Inc.
Inventor： Kyung Hoon KIM , Myeong Jae PARK , Woo Yeol SHIN , Sung Eun LEE , Han Kyu CHI , Jae Won HAN
CPC classification number: H03L7/07 , G11C7/1093 , G11C7/222 , H03L7/0805 , H03L7/0814 , H03L7/0816 , H03L7/091 , H03M9/00
Abstract: A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.
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