公开(公告)号：US09516247B2

公开(公告)日：2016-12-06

申请号：US14490386

申请日：2014-09-18

Applicant: SK hynix Inc.

Inventor： Min-Seok Shin ,  Young-Chul Sohn

IPC: H04N5/355 ,  H04N5/374 ,  H04N9/04 ,  H04N5/378

CPC classification number: H04N5/35581 ,  H04N5/35554 ,  H04N5/374 ,  H04N5/378 ,  H04N9/045

Abstract: An image sensing device includes a unit pixel including one or more first sub-pixels of a white color and a plurality of second sub-pixels of a color other than the white color in a matrix, a row control block suitable for controlling the first and second sub-pixels to output sequentially first and second pixel signals during one row unit time, and an image process block suitable for processing the first and second pixel signal's.

Abstract translation: 图像感测装置包括：单位像素，包括一个或多个白色的第一子像素和多个第二子像素，所述第二子像素具有矩阵中的白色以外的颜色;行控制块，适于控制第一和 第二子像素，用于在一行单位时间期间顺序地输出第一和第二像素信号，以及适于处理第一和第二像素信号的图像处理块。

公开(公告)号：US09184753B2

公开(公告)日：2015-11-10

申请号：US14329599

申请日：2014-07-11

Applicant: SK hynix Inc.

Inventor： Min-Seok Shin

IPC: H03M1/34 ,  H03K21/02 ,  H04N5/3745 ,  H04N5/369 ,  H03K21/38 ,  H03K23/50

CPC classification number: H03K21/023 ,  H03K21/026 ,  H03K21/38 ,  H03K23/50 ,  H03M1/34 ,  H03M1/56 ,  H04N5/3698 ,  H04N5/37455 ,  H04N5/378

Abstract: A double data rate (DDR) counter includes a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block; a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (LSB+1) bit or higher; a third control block suitable for determining an enable period of the counting block; the sampling block suitable for sampling a state of the clock signal and outputting an LSB value, when an input signal transits; and the counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (LSB+1) bit or higher.

Abstract translation: 双数据速率（DDR）计数器包括适于根据计数模式信号和采样块的先前状态值切换计数器时钟的第一控制块; 适于确定是否切换输入到与（LSB + 1）位或更高位相对应的计数块的时钟信号的第二控制块; 适于确定所述计数块的使能周期的第三控制块; 所述采样块适于对所述时钟信号的状态进行采样，并且当输入信号转换时输出LSB值; 以及适合于根据第二和第三控制块的输出信号执行计数的计数块，并输出具有（LSB + 1）位或更高位的计数器输出信号。

公开(公告)号：US08922403B2

公开(公告)日：2014-12-30

申请号：US14051102

申请日：2013-10-10

Applicant: Industry-University Cooperation Foundation Hanyang University ,  SK hynix Inc.

Inventor： Ja-Seung Gou ,  Oh-Kyong Kwon ,  Min-Seok Shin ,  Min-Kyu Kim

IPC: H03M1/06 ,  H03M3/00

CPC classification number: H03M1/0607 ,  H03M1/007 ,  H03M1/56 ,  H03M1/58

Abstract: An analog-to-digital conversion circuit includes an analog-to-digital conversion unit configured to analog-to-digital convert an input voltage and generate a digital signal, a resolution control unit configured to: set a resolution of the analog-to-digital conversion unit to N (N is the natural number) bits, in a case where the input voltage is smaller than a first voltage, and set the resolution of the analog-to-digital conversion unit to N−M (1≦M

Abstract translation: 模拟数字转换电路包括被配置为模数转换输入电压并产生数字信号的模数转换单元，分辨率控制单元，被配置为：将模拟 - 在输入电压小于第一电压的情况下，将数字转换单元设置为N（N为自然数）位，并将模数转换单元的分辨率设置为N-M（1＆nl; M＆ 在输入电压大于第一电压的情况下，N，M是自然数）比特;以及信号校正单元，被配置为：在第一电压和第二电压之间产生校正的数字信号，基于边界值和数字信号， 数字信号的值大于边界值，并且输入电压小于第一电压。

公开(公告)号：US09967495B2

公开(公告)日：2018-05-08

申请号：US15177765

申请日：2016-06-09

Applicant: SK hynix Inc.

Inventor： Min-Seok Shin

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/3745 ,  H04N5/365

CPC classification number: H04N5/37457 ,  H04N5/3653

Abstract: An image sensing device includes a plurality of pixel groups, each pixel group including two or more neighboring pixels, and a controller suitable for controlling the pixel groups on a basis of a frame unit, wherein a readout order of the pixels in each of the pixel groups is different between present and next frames.

公开(公告)号：US09628726B2

公开(公告)日：2017-04-18

申请号：US14491707

申请日：2014-09-19

Applicant: SK hynix Inc.

Inventor： Min-Seok Shin

IPC: H04N5/238 ,  H04N5/335 ,  H04N5/235 ,  H04N5/355 ,  H04N5/374 ,  H04N5/378 ,  H04N9/04

CPC classification number: H04N5/35572 ,  H04N5/35554 ,  H04N5/374 ,  H04N5/378 ,  H04N9/045

Abstract: An image sensing device includes: a pixel unit including a first sub-pixel and a second sub-pixel corresponding to a single color; a row control block suitable for controlling exposure times of the first and second sub-pixels differently from one another during an exposure time section, and controlling a first sub-pixel signal and a second sub-pixel signal to be outputted from the first and second sub-pixels during a single row line unit time during a read time section; and an image process block suitable for generating three or more image data which have different exposure times based on the first and second sub-pixel signals.

公开(公告)号：US08717217B2

公开(公告)日：2014-05-06

申请号：US13718653

申请日：2012-12-18

Applicant: SK hynix Inc.

Inventor： Ja-Seung Gou ,  Oh-Kyong Kwon ,  Min-Seok Shin ,  Min-Kyu Kim

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/162 ,  H03M1/466

Abstract: An analog-to-digital converter includes a comparison unit that outputs a result obtained by comparing a voltage of an input node with a comparison voltage; 1st to Nth capacitors having one ends connected to the input node, respectively; and 1st to N−1th voltage selection units corresponds to the 2nd to Nth capacitors, respectively and applies one of a voltages of a 1st node, a 2nd node, and the comparison voltage to the other ends of the corresponding capacitors. An input signal is sampled to the input node, the 1st to N−1th voltage selection units select one of the voltages of the 2 nodes and convert a part of the input signal into a 1st digital signal, and the 1st to N−1th voltage selection units select one of the voltages of the 2 nodes and convert the remaining part of the input signal into a 2nd digital signal.

Abstract translation: 模数转换器包括比较单元，其输出通过将输入节点的电压与比较电压进行比较而获得的结果; 分别具有一端连接到输入节点的第1至第N电容器; 第1〜第N电压选择单元分别对应于第2〜第N电容器，并将相应的电容器的另一端施加第1节点，第2节点和第2节点的电压中的一个。 输入信号被采样到输入节点，第1到第N-1个电压选择单元选择2个节点中的一个电压，并将一部分输入信号转换为第1数字信号，第1至第N-1个电压 选择单元选择2个节点的一个电压，并将输入信号的剩余部分转换为第二个数字信号。

公开(公告)号：US10896701B2

公开(公告)日：2021-01-19

申请号：US16236963

申请日：2018-12-31

Applicant: SK hynix Inc.

Inventor： Min-Seok Shin

IPC: G11C7/00 ,  G11C7/10 ,  H01L27/146 ,  G11C11/4096 ,  G11C7/12

Abstract: A data readout apparatus may include a counter array including an address decoder and a counter circuit, the address decoder being configured to receive an address, the counter circuit being coupled to the address decoder and perform a counting operation based on a column address, a sense amplifier array coupled to the counter array to read out the data from the counter array, a clock driver arranged adjacent to the center of the counter array to distribute clock pulses, a first precharge circuit arranged at one side of the counter array and structured to receive the clock pulses from the clock driver and perform a precharge operation, and a second precharge circuit arranged at the other side of the counter array and structured to receive the clock pulses from the clock driver and perform the precharge operation.

公开(公告)号：US20200082853A1

公开(公告)日：2020-03-12

申请号：US16236963

申请日：2018-12-31

Applicant: SK hynix Inc.

Inventor： Min-Seok Shin

IPC: G11C7/10 ,  G11C7/12 ,  G11C11/4096 ,  H01L27/146

Abstract: A data readout apparatus may include a counter array including an address decoder and a counter circuit, the address decoder being configured to receive an address, the counter circuit being coupled to the address decoder and perform a counting operation based on a column address, a sense amplifier array coupled to the counter array to read out the data from the counter array, a clock driver arranged adjacent to the center of the counter array to distribute clock pulses, a first precharge circuit arranged at one side of the counter array and structured to receive the clock pulses from the clock driver and perform a precharge operation, and a second precharge circuit arranged at the other side of the counter array and structured to receive the clock pulses from the clock driver and perform the precharge operation.

公开(公告)号：US10057525B2

公开(公告)日：2018-08-21

申请号：US14919166

申请日：2015-10-21

Applicant: SK hynix Inc.

Inventor： Min-Seok Shin

IPC: H04N5/378 ,  H04N5/376

CPC classification number: H04N5/378 ,  H04N5/3765

Abstract: An image sensing device includes a read-out control block suitable for generating a selection address signal and one or more address clock signals based on a source address signal, and a judge clock signal having a higher frequency than a source clock signal; and a read-out block suitable for reading out a plurality of pixel signals in response to the selection address signal, the address clock signals and the judge clock signal.

公开(公告)号：US11070759B2

公开(公告)日：2021-07-20

申请号：US14921092

申请日：2015-10-23

Applicant: SK hynix Inc.

Inventor： Min-Seok Shin

IPC: H04N5/378 ,  H04N5/369 ,  H04N5/374 ,  H04N5/3745 ,  H04N5/335

Abstract: An image sensing device includes a pixel suitable for outputting a pixel signal through a read-out line during a read-out section and a precharge block suitable for precharging the read-out line to a voltage level corresponding to an initial voltage level of the pixel signal during a row non-selection section adjacent to the read-out section.