公开(公告)号：US20150117079A1

公开(公告)日：2015-04-30

申请号：US14590503

申请日：2015-01-06

申请人： SK hynix Inc.

发明人： Tae Sik YUN ,  Dong Hwee KIM

IPC分类号： G11C8/08 ,  G11C5/02

CPC分类号： G11C8/08 ,  G11C5/02 ,  G11C11/4085 ,  G11C11/4097

摘要： A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.

摘要翻译： 提供了一种副字线驱动器和具有该子字线驱动器的半导体集成电路器件。 半导体集成电路器件包括相邻的四个子字线驱动器，其配置为响应于四个主字线的信号驱动四个子字线，其中相邻子字线驱动器的第一和第二子字线驱动器彼此共享一个保持器晶体管 ，并且相邻子字线驱动器的第三和第四子字线驱动器彼此共享一个保持器晶体管。

公开(公告)号：US20140063990A1

公开(公告)日：2014-03-06

申请号：US13720741

申请日：2012-12-19

申请人： SK HYNIX INC.

发明人： Young Jun KU ,  Tae Sik YUN

IPC分类号： G11C7/10

CPC分类号： G11C7/1051 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1069 ,  G11C2207/005

摘要： A multi-chip semiconductor apparatus includes a plurality of semiconductor chips which are electrically connected through a plurality of through-chip vias (TSVs) and stacked, wherein each of the semiconductor chips includes: a first data input/output line configured to transmit data for a first memory bank; a second data input/output line configured to transmit data for a second memory bank; and a data transmitting/receiving (TX/RX) unit configured to electrically connect any one of the first and second data input/output lines to a first TSV in response to selected memory bank information, during read and write operations for the corresponding semiconductor chip.

摘要翻译： 多芯片半导体装置包括通过多个贯通芯片通孔（TSV）电连接并堆叠的多个半导体芯片，其中每个半导体芯片包括：第一数据输入/输出线，被配置为传送数据， 第一个记忆库 第二数据输入/输出线，被配置为发送第二存储体的数据; 以及数据发送/接收（TX / RX）单元，被配置为在对应的半导体芯片的读取和写入操作期间响应于选择的存储体信息将第一和第二数据输入/输出线中的任何一个电连接到第一TSV 。

公开(公告)号：US20190172547A1

公开(公告)日：2019-06-06

申请号：US16051796

申请日：2018-08-01

申请人： SK hynix Inc.

发明人： Tae Sik YUN ,  Chun Seok JEONG

IPC分类号： G11C29/44 ,  G11C29/36 ,  G11C29/42

摘要： A memory system and a method for operating the same, wherein the memory system includes a first memory and a second memory each configured to store data. The memory system further includes a test and repair circuit operationally connected to the first memory and to the second memory. The test and repair circuit is configured to receive a test initiation signal and perform, in response to receiving the test initiation signal, a test operation on at least one of the first memory and the second memory. The test and repair circuit is also configured to perform, based on a result of the test operation, a repair operation on the at least one of the first memory and the second memory.

公开(公告)号：US20160111399A1

公开(公告)日：2016-04-21

申请号：US14981284

申请日：2015-12-28

申请人： SK hynix Inc.

发明人： Tae Sik YUN ,  Sang Jin BYEON

IPC分类号： H01L25/065 ,  H03K17/14

CPC分类号： H01L25/0657 ,  G01R31/2882 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H03K17/14 ,  H03K19/00369 ,  Y10T307/826

摘要： A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the to replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed is through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

摘要翻译： 半导体装置包括：从芯片，包括信号传送单元，配置为响应于芯片选择信号确定是否传送输入信号; 包括具有与信号传送单元相同的配置的复制电路单元的主芯片和被配置为接收信号传送单元的输出信号和复制电路单元的输出信号的信号输出单元，并响应于响应而产生输出信号 到控制信号; 通过垂直形成的从芯片的第一通芯片，并且一端连接到主芯片以接收输入信号，另一端连接到信号传送单元; 并且垂直形成的第二通芯片通过从芯片，并且其一端连接到信号传送单元，另一端连接到信号输出单元。

公开(公告)号：US20220406399A1

公开(公告)日：2022-12-22

申请号：US17490443

申请日：2021-09-30

申请人： SK hynix Inc.

发明人： A Ram RIM ,  Tae Sik YUN

IPC分类号： G11C29/00

摘要： A semiconductor device includes a memory bank including a first memory block, a second memory block, and a redundancy memory block, and a column line selection circuit configured, when a fail occurs in a first column line of the first memory block, to replace the first column line of the first memory block with a first redundancy line of the redundancy memory block, and replace a second column line of the second memory block with a second redundancy line of the redundancy memory block.

公开(公告)号：US20150162064A1

公开(公告)日：2015-06-11

申请号：US14243651

申请日：2014-04-02

申请人： SK HYNIX INC.

发明人： Sang Mook OH ,  Tae Sik YUN

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C8/04 ,  G11C8/18 ,  G11C11/4072 ,  G11C11/4087 ,  G11C29/04 ,  G11C29/783 ,  G11C2029/4402 ,  G11C2211/4065

摘要： A refresh control circuit of a semiconductor apparatus includes a repair address processing unit configured to compare refresh addresses and repair information, activate a redundant enable signal, and convert the semiconductor apparatus into the same operation state as an initialization state of the repair information in response to activation of a repair initialization signal; a refresh counter configured to count the refresh addresses extended to a signal bit in response to activation of a redundant count enable signal; and a refresh control unit configured to activate the repair initialization signal and the redundant count enable signal when an additional refresh mode is set in response to a refresh command.

摘要翻译： 半导体装置的刷新控制电路包括修复地址处理单元，被配置为比较刷新地址和修复信息，激活冗余使能信号，并且将半导体装置转换为与修复信息的初始化状态相同的操作状态，以响应于 激活修复初始化信号; 刷新计数器，配置为响应于冗余计数使能信号的激活而对扩展到信号位的刷新地址进行计数; 以及刷新控制单元，被配置为当响应于刷新命令设置附加刷新模式时，激活修复初始化信号和冗余计数使能信号。

公开(公告)号：US20130157386A1

公开(公告)日：2013-06-20

申请号：US13760342

申请日：2013-02-06

申请人： SK HYNIX INC.

发明人： Tae Sik YUN ,  Won Woong SEOK

IPC分类号： H01L21/66

CPC分类号： H01L22/14 ,  G01R31/318513 ,  H01L22/22 ,  Y10T29/49004 ,  Y10T29/53022 ,  Y10T29/53174 ,  Y10T29/53265

摘要： A semiconductor apparatus includes a semiconductor chip through-line for transmitting signals commonly to a plurality of stacked semiconductor chips. The apparatus includes a first test pulse signal transmission unit configured to transmit a first test pulse signal to a first end of the semiconductor chip through-line when a power-up operation is performed; a second test pulse signal transmission unit configured to transmit a second test pulse signal to a second end of the semiconductor chip through-line after the first test pulse signal is transmitted; a first signal reception unit coupled to the first end of the semiconductor chip through-line, and configured to receive signals transmitted from the first and second test pulse signal transmission units; and a second signal reception unit coupled to the second end of the semiconductor chip through-line, and configured to receive the signals transmitted by the first and second test pulse signal transmission units.

摘要翻译： 半导体装置包括用于将信号共同地传输到多个堆叠的半导体芯片的半导体芯片直通线。 该装置包括：第一测试脉冲信号发送单元，被配置为当执行上电操作时将第一测试脉冲信号发送到半导体芯片通过线的第一端; 第二测试脉冲信号发送单元，被配置为在发送所述第一测试脉冲信号之后将第二测试脉冲信号发送到所述半导体芯片直通线的第二端; 第一信号接收单元，耦合到半导体芯片通过线的第一端，并且被配置为接收从第一和第二测试脉冲信号传输单元发送的信号; 以及第二信号接收单元，其耦合到半导体芯片贯穿线的第二端，并且被配置为接收由第一和第二测试脉冲信号传输单元发送的信号。