公开(公告)号：US10790034B2

公开(公告)日：2020-09-29

申请号：US16128239

申请日：2018-09-11

申请人： SK hynix Inc.

发明人： Min Ho Her ,  Seung Il Kim ,  Yong Ho Kim ,  Jae Min Lee ,  Seon Young Choi

IPC分类号： G11C16/00 ,  G11C29/52 ,  G06F11/10 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56

摘要： Provided herein may be a memory device, a memory system having the memory device, and a method of operating the memory device. The memory device may include a memory cell array configured to store data, a peripheral circuit configured to perform a program operation on the memory cell array, and a control logic configured to perform the program operation by controlling the peripheral circuit and to perform a status check operation after the program operation. Here, the control logic may be configured to, based on a determination that the status check operation has passed, perform a number-of-program pulses comparison operation by comparing a number of program pulses used in the program operation to a first preset range.

公开(公告)号：US09997216B2

公开(公告)日：2018-06-12

申请号：US15442067

申请日：2017-02-24

申请人： TOSHIBA MEMORY CORPORATION ,  SK HYNIX INC.

发明人： Yutaka Shirai ,  Naoki Shimizu ,  Kenji Tsuchida ,  Yoji Watanabe ,  Ji Hyae Bae ,  Yong Ho Kim

IPC分类号： G11C8/00 ,  G11C7/12 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/16 ,  G11C7/22 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/1039 ,  G11C7/222 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.

公开(公告)号：US10910070B2

公开(公告)日：2021-02-02

申请号：US16238256

申请日：2019-01-02

申请人： SK hynix Inc.

发明人： Min Ho Her ,  Dong Hyun Kim ,  Seung Il Kim ,  Yong Ho Kim ,  Jae Min Lee ,  Seon Young Choi

IPC分类号： G11C16/08 ,  G11C16/28 ,  G11C16/16 ,  G11C11/56 ,  G11C16/34 ,  G06F12/02 ,  G06F3/06 ,  G06F12/0866

摘要： The present disclosure relates to an electronic device. A storage device includes a memory device configured to include a plurality of memory cells and a memory controller configured to determine a read voltage for a read operation to be performed on the memory device according to whether the read operation is a cache read operation.

公开(公告)号：US11107538B2

公开(公告)日：2021-08-31

申请号：US17134786

申请日：2020-12-28

申请人： SK hynix Inc.

发明人： Min Ho Her ,  Dong Hyun Kim ,  Seung Il Kim ,  Yong Ho Kim ,  Jae Min Lee ,  Seon Young Choi

IPC分类号： G11C16/08 ,  G11C16/28 ,  G11C16/16 ,  G11C11/56 ,  G11C16/34 ,  G06F12/02 ,  G06F3/06 ,  G06F12/0866

摘要： The present disclosure relates to an electronic device. A storage device includes a memory device configured to include a plurality of memory cells and a memory controller configured to determine a read voltage for a read operation to be performed on the memory device according to whether the read operation is a cache read operation.