公开(公告)号：US09997216B2

公开(公告)日：2018-06-12

申请号：US15442067

申请日：2017-02-24

申请人： TOSHIBA MEMORY CORPORATION ,  SK HYNIX INC.

发明人： Yutaka Shirai ,  Naoki Shimizu ,  Kenji Tsuchida ,  Yoji Watanabe ,  Ji Hyae Bae ,  Yong Ho Kim

IPC分类号： G11C8/00 ,  G11C7/12 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/16 ,  G11C7/22 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/1039 ,  G11C7/222 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.

公开(公告)号：USRE46920E1

公开(公告)日：2018-06-26

申请号：US14612000

申请日：2015-04-28

申请人： Toshiba Memory Corporation

发明人： Katsuyuki Fujita ,  Kenji Tsuchida

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C11/16

CPC分类号： G11C13/004 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2013/0054

摘要： According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle at a level in between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.

公开(公告)号：US10658063B2

公开(公告)日：2020-05-19

申请号：US16123558

申请日：2018-09-06

申请人： TOSHIBA MEMORY CORPORATION

发明人： Hiromi Noro ,  Kenji Tsuchida

IPC分类号： G11C16/04 ,  G11C29/04 ,  G11C11/16 ,  G11C29/52

摘要： According to one embodiment, a semiconductor memory device includes a memory cell, a read circuit, a correcting circuit and a write circuit. The read circuit is configured to read first data from the memory cell by receiving a first command. The correcting circuit is configured to generate second data by correcting an error included in the first data. The write circuit is configured to write the second data to the memory cell in response to receiving a second command.

公开(公告)号：USRE46702E1

公开(公告)日：2018-02-06

申请号：US14794707

申请日：2015-07-08

申请人： TOSHIBA MEMORY CORPORATION

发明人： Katsuhiko Hoya ,  Kenji Tsuchida

IPC分类号： G11C11/00 ,  G11C11/16

CPC分类号： G11C11/1693 ,  G11C11/1675

摘要： A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device includes multiplexers between the bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier, and write amplifiers that are located corresponding to memory cell blocks each of which includes memory cells each including the magnetic tunnel junction element and the transistor and are connected to the bit lines or connected via the multiplexers to the bit lines. To write data, the sense amplifier applies a write voltage to the bit lines and then the write amplifiers hold the write voltage.