公开(公告)号：US11961908B2

公开(公告)日：2024-04-16

申请号：US17462765

申请日：2021-08-31

申请人： SK hynix Inc.

发明人： Young Gwang Yoon

IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/66969 ,  H01L29/24

摘要： Various embodiments of the present invention disclosure are directed to a vertical transistor having different doping profiles in its upper channel layer and lower channel layer for reducing leakage current while enhancing contact resistance and a method for manufacturing the vertical transistor.
According to an embodiment of the present invention disclosure, a semiconductor device comprises a lower contact, a vertical channel layer on the lower contact, the vertical channel layer including a metal component and an oxygen component, and an upper contact on the vertical channel layer. The vertical channel layer has a gradual doping profile in which a doping concentration of the metal component is lowest in an intermediate region and gradually increases from the intermediate region to the upper contact.

公开(公告)号：US12033858B2

公开(公告)日：2024-07-09

申请号：US17534252

申请日：2021-11-23

申请人： SK hynix Inc.

发明人： Young Gwang Yoon

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L29/423

CPC分类号： H01L21/28097 ,  H01L21/28088 ,  H01L21/823443 ,  H01L29/42372

摘要： A method for fabricating a MOS transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.

公开(公告)号：US11848383B2

公开(公告)日：2023-12-19

申请号：US17463240

申请日：2021-08-31

申请人： SK hynix Inc.

发明人： Young Gwang Yoon

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/165

CPC分类号： H01L29/7851 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795

摘要： Various embodiments of the present invention are to provide a semiconductor device and a method for fabricating the same and, more particularly, to a semiconductor device including isolation layers including an air gap, thereby minimizing stress to a substrate caused by oxide and improving performance of a device, and a method for fabricating the same. The semiconductor device according to the embodiment of the present invention comprises: a plurality of isolation layers each including a trench formed in a substrate and an air gap in a lower portion of the trench; an active region including a fin body disposed between the isolation layers, which are consecutively disposed, and a fin formed on the fin body, the fin having a narrower width than the fin body and extending in a first direction; a gate structure partially covering the active region and the isolation layers, and extending in a second direction; and a source/drain region covering the fin on both sides of the gate structure.

公开(公告)号：US11942544B2

公开(公告)日：2024-03-26

申请号：US17481479

申请日：2021-09-22

申请人： SK hynix Inc.

发明人： Young Gwang Yoon

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/66666

摘要： A semiconductor device includes: a first stacked structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked vertically; a second stacked structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked vertically, and having a first side facing a first side of the first stacked structure; a first channel layer formed on the first side of the first stacked structure; a second channel layer formed on the first side of the second stacked structure; a lower electrode layer commonly coupled to lower ends of the first and second channel layers between the first and second stacked structures; a first upper electrode layer coupled to an upper end of the first channel layer; and a second upper electrode layer coupled to an upper end of the second channel layer.

公开(公告)号：US11935934B2

公开(公告)日：2024-03-19

申请号：US17502737

申请日：2021-10-15

申请人： SK hynix Inc.

发明人： Young Gwang Yoon

IPC分类号： H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40 ,  H01L29/51

CPC分类号： H01L29/4236 ,  H01L21/022 ,  H01L21/76849 ,  H01L21/7685 ,  H01L29/401 ,  H01L29/513

摘要： The present invention provides a semiconductor device including a capping layer of a reduced thickness and capable of preventing regrowth of an interface layer caused by oxygen injection, and a method for fabricating the same. According to an embodiment of the present invention, the semiconductor device comprises: an interface layer on a substrate; a high-k layer on the interface layer; a gate electrode on the high-k layer; and a capping layer including a first oxygen barrier layer and a second oxygen barrier layer on the gate electrode.