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    Method for manufacturing a structure for forming a tridimensional monolithic integrated circuit
    1.
    发明授权
    Method for manufacturing a structure for forming a tridimensional monolithic integrated circuit 有权

    公开(公告)号：US11205702B2

    公开(公告)日：2021-12-21

    申请号：US16086275

    申请日：2017-03-31

    Applicant: Soitec

    Inventor： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

    IPC: H01L29/161 ,  H01L23/00 ,  H01L21/306

    Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

    Semiconductor structures including stacks of indium gallium nitride layers
    2.
    发明授权
    Semiconductor structures including stacks of indium gallium nitride layers 有权
    包括氮化铟镓层的叠层的半导体结构

    公开(公告)号：US09276070B2

    公开(公告)日：2016-03-01

    申请号：US14250096

    申请日：2014-04-10

    Applicant: Soitec

    Inventor： Christophe Figuet ,  Pierre Tomasini

    IPC: H01L33/04 ,  H01L29/205 ,  C30B25/02 ,  C30B29/40 ,  H01L21/02

    CPC classification number: H01L29/205 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0259 ,  H01L33/04

    Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

    Abstract translation: 形成三元III族氮化物材料的方法包括在室中的衬底上的外延生长三元III族氮化物材料。 外延生长包括在室内提供前体气体混合物，其包括氮气前体的分压与腔室中一种或多种III族前体的分压的相对高的比例。 至少部分地由于相对高的比例，可以将三元III族氮化物材料层生长到具有小的V凹坑缺陷的高最终厚度。 使用这种方法制造包括这种三元III族氮化物材料层的半导体结构。

    SEMICONDUCTOR STRUCTURES INCLUDING STACKS OF INDIUM GALLIUM NITRIDE LAYERS
    3.
    发明申请
    SEMICONDUCTOR STRUCTURES INCLUDING STACKS OF INDIUM GALLIUM NITRIDE LAYERS 审中-公开
    半导体结构包括氮化镓层的堆叠

    公开(公告)号：US20140217419A1

    公开(公告)日：2014-08-07

    申请号：US14250096

    申请日：2014-04-10

    Applicant: Soitec

    Inventor： Christophe Figuet ,  Pierre Tomasini

    IPC: H01L29/205

    CPC classification number: H01L29/205 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0259 ,  H01L33/04

    Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

    Abstract translation: 形成三元III族氮化物材料的方法包括在室中的衬底上的外延生长三元III族氮化物材料。 外延生长包括在室内提供前体气体混合物，其包括氮气前体的分压与腔室中一种或多种III族前体的分压的相对高的比例。 至少部分地由于相对高的比例，可以将三元III族氮化物材料层生长到具有小的V凹坑缺陷的高最终厚度。 使用这种方法制造包括这种三元III族氮化物材料层的半导体结构。

    METHOD FOR MANUFACTURING A STRUCTURE FOR FORMING A TRIDIMENSIONAL MONOLITHIC INTEGRATED CIRCUIT
    4.
    发明申请
    METHOD FOR MANUFACTURING A STRUCTURE FOR FORMING A TRIDIMENSIONAL MONOLITHIC INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200295138A1

    公开(公告)日：2020-09-17

    申请号：US16086275

    申请日：2017-03-31

    Applicant: Soitec

    Inventor： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

    IPC: H01L29/161 ,  H01L23/00

    Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

    DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIALS, AND RELATED STRUCTURES
    5.
    发明申请
    DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIALS, AND RELATED STRUCTURES 有权
    用于形成III / V半导体材料的沉积方法及相关结构

    公开(公告)号：US20130049012A1

    公开(公告)日：2013-02-28

    申请号：US13659521

    申请日：2012-10-24

    Applicant: Soitec ,  Christophe Figuet ,  Pierre Tomasini

    Inventor： Christophe Figuet ,  Pierre Tomasini

    IPC: H01L29/205

    CPC classification number: H01L29/205 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0259 ,  H01L33/04

    Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

    Abstract translation: 形成三元III族氮化物材料的方法包括在室中的衬底上的外延生长三元III族氮化物材料。 外延生长包括在室内提供前体气体混合物，其包括氮气前体的分压与腔室中一种或多种III族前体的分压的相对高的比例。 至少部分地由于相对高的比例，可以将三元III族氮化物材料层生长到具有小的V凹坑缺陷的高最终厚度。 使用这种方法制造包括这种三元III族氮化物材料层的半导体结构。

    Deposition methods for the formation of III/V semiconductor materials, and related structures
    7.
    发明授权
    Deposition methods for the formation of III/V semiconductor materials, and related structures 有权
    用于形成III / V半导体材料的沉积方法及相关结构

    公开(公告)号：US08742428B2

    公开(公告)日：2014-06-03

    申请号：US13659521

    申请日：2012-10-24

    Applicant: Soitec ,  Christophe Figuet ,  Pierre Tomasini

    Inventor： Christophe Figuet ,  Pierre Tomasini

    IPC: H01L29/15

    CPC classification number: H01L29/205 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0259 ,  H01L33/04

    Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

    Abstract translation: 形成三元III族氮化物材料的方法包括在室中的衬底上的外延生长三元III族氮化物材料。 外延生长包括在室内提供前体气体混合物，其包括氮气前体的分压与腔室中一种或多种III族前体的分压的相对高的比例。 至少部分地由于相对高的比例，可以将三元III族氮化物材料层生长到具有小的V凹坑缺陷的高最终厚度。 使用这种方法制造包括这种三元III族氮化物材料层的半导体结构。

    SEMICONDUCTOR STRUCTURE FOR OPTOELECTRONIC APPLICATIONS
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE FOR OPTOELECTRONIC APPLICATIONS 有权

    公开(公告)号：US20240429683A1

    公开(公告)日：2024-12-26

    申请号：US18685257

    申请日：2022-09-08

    Applicant: SOITEC

    Inventor： Christophe Figuet ,  Isabelle Huyet

    IPC: H01S5/183

    Abstract: A semiconductor structure for optoelectronic applications; comprises a first layer made of a crystalline semiconductor, the layer being disposed on an intermediate layer including or adjacent to a direct-bonding interface, the intermediate layer being disposed on a second layer made of a crystalline semiconductor material. The intermediate layer is composed of a material that is different from those of the first and second layers, and the attenuation coefficient of which is lower than 100. The refractive index of the intermediate layer differs by less than 0.3 from the refractive index of at least one sub-layer of the first layer adjacent to the intermediate layer, and of at least one sub-layer of the second layer adjacent to the intermediate layer.

    Method for separating at least two substrates along a selected interface
    10.
    发明授权
    Method for separating at least two substrates along a selected interface 有权

    公开(公告)号：US10093086B2

    公开(公告)日：2018-10-09

    申请号：US15256265

    申请日：2016-09-02

    Applicant: Soitec

    Inventor： Didier Landru ,  Christophe Figuet

    IPC: H01L21/762 ,  H01L21/67 ,  B32B43/00 ,  H01L21/20 ,  H01L21/683

    Abstract: A process for separating at least two substrates comprising at least two separation interfaces along one of the interfaces includes, before inserting a blade between the substrate, damaging at least one portion of a peripheral region of a chosen one of the interfaces, then inserting the blade and partially parting the substrates, and applying a fluid in a space between the parted substrates while the blade remains inserted therebetween, and decreasing a rupture energy of the chosen interface by stress corrosion involving breaking of siloxane bonds present at the interface.

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