公开(公告)号：US20250096095A1

公开(公告)日：2025-03-20

申请号：US18468957

申请日：2023-09-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Peik Eng Ooi ,  Beng Yee Teh ,  Linda Pei Ee Chua

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die to form a reconstituted wafer. A first insulating layer is formed over the reconstituted wafer. A first dummy opening is formed in the first insulating layer. A first conductive layer is formed on the first insulating layer including a first contact pad over the first dummy opening.

公开(公告)号：US20250054902A1

公开(公告)日：2025-02-13

申请号：US18448913

申请日：2023-08-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Peik Eng Ooi

IPC: H01L23/00 ,  H01L23/495

Abstract: A semiconductor device has an electrical component with bump structures. A conductive layer is formed over the electrical component with a first segment of the conductive layer coupled between the first and second bumps. The electrical component is disposed on a paddle of a lead frame interposer. A first bond wire is coupled between a first lead and the first bump. A second bond wire is coupled between a second lead and the second bump. A third bond wire is coupled between a third lead and a third bump, and a fourth bond wire is coupled between a fourth lead and a fourth bump. A fifth bond wire coupled between the second lead and third lead and a second segment of the conductive layer is coupled between the third bump and fourth bump to constitute a daisy chain loop to test continuity of the bump structures.

公开(公告)号：US20240355760A1

公开(公告)日：2024-10-24

申请号：US18302503

申请日：2023-04-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Peik Eng Ooi ,  Gai Leong Lai

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/19 ,  H01L2224/2105 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: A semiconductor device has a substrate and a first RDL formed over the substrate. A second RDL is formed over the first RDL with a first conductive via electrically connecting the first RDL and second RDL and a first opening formed in the second RDL around the first conductive via for stress relief. The first opening formed in the second RDL can have a semi-circle shape or a plurality of semi-circles or segments. A third RDL is formed over the second RDL with a second conductive via electrically connecting the second RDL and third RDL and a second opening formed in the third RDL around the second conductive via for stress relief. The first opening is offset from the second opening. A plurality of first openings can be formed around the first conductive via for stress relief, each offset from one another.

公开(公告)号：US20240055374A1

公开(公告)日：2024-02-15

申请号：US17819738

申请日：2022-08-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Peik Eng Ooi ,  Lee Sun Lim

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L24/11 ,  H01L2224/02235 ,  H01L2224/03013 ,  H01L2224/0401 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/02311 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/13124 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13116 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/11849

Abstract: A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.