公开(公告)号：US10216965B2

公开(公告)日：2019-02-26

申请号：US15109747

申请日：2014-12-23

Applicant: STC.UNM ,  Case Western Reserve University

Inventor： James Plusquellic ,  Swarup Bhunia

IPC: G06F21/75 ,  G11C23/00 ,  G06F7/58 ,  H04L9/08 ,  G09C1/00 ,  G06F21/60 ,  G11C13/00 ,  G11C16/10 ,  G11C16/26

Abstract: This disclosure describes techniques for generating physically unclonable functions (PUF) from non-volatile memory cells. The PUFs leverage resistance variations in non-volatile memory cells. Resistance variations in array of non-volatile memory cells may be produce a bitstring during an enrollment process. The bitstring may be stored in the non-volatile memory array. Regeneration may include retrieving the bitstring from the non-volatile memory array.

公开(公告)号：US20160328578A1

公开(公告)日：2016-11-10

申请号：US15109747

申请日：2014-12-23

Applicant: STC.UNM ,  CASE WESTERN RESERVE UNIVERSITY

Inventor： James Plusquellic ,  Swarup Bhunia

IPC: G06F21/75 ,  G06F21/60 ,  G11C16/26 ,  G11C13/00 ,  G11C23/00 ,  G11C16/10

CPC classification number: G06F21/75 ,  G06F7/588 ,  G06F21/604 ,  G09C1/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C23/00 ,  H04L9/0866 ,  H04L2209/12

Abstract: This disclosure describes techniques for generating physically unclonable functions (PUF) from non-volatile memory cells. The PUFs leverage resistance variations in non-volatile memory cells. Resistance variations in array of non-volatile memory cells may be produce a bitstring during an enrollment process. The bitstring may be stored in the non-volatile memory array. Regeneration may include retrieving the bitstring from the non-volatile memory array.

Abstract translation: 本公开描述了用于从非易失性存储器单元生成物理不可克隆功能（PUF）的技术。 PUF利用非易失性存储单元中的电阻变化。 非易失性存储器单元阵列中的电阻变化可能在注册过程中产生位串。 位串可以存储在非易失性存储器阵列中。 再生可以包括从非易失性存储器阵列检索位串。

公开(公告)号：US11132178B2

公开(公告)日：2021-09-28

申请号：US16856887

申请日：2020-04-23

Applicant: STC.UNM

Inventor： James Plusquellic

IPC: G06F7/58 ,  H04L9/00 ,  H04L9/08 ,  G09C1/00

Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.

公开(公告)号：US10956557B2

公开(公告)日：2021-03-23

申请号：US16067757

申请日：2017-01-11

Applicant: STC.UNM

Inventor： James Plusquellic ,  Wenjie Che ,  Dylan Ismari

IPC: G06F21/44 ,  G06F21/70 ,  G06F21/30 ,  G06F21/73 ,  H04L9/08 ,  H04L9/32 ,  H04L9/06 ,  G06F7/58 ,  G06F21/34

Abstract: An authentication protocol using a Hardware-Embedded Delay PUF (“HELP”), which derives randomness from within-die path delay variations that occur along the paths within a hardware implementation of a cryptographic primitive, for example, the Advanced Encryption Standard (“AES”) algorithm or Secure Hash Algorithm 3 (“SHA-3”). The digitized timing values which represent the path delays are stored in a database on a secure server (verifier) as an alternative to storing PUF response bitstrings thereby enabling the development of an efficient authentication protocol that provides both privacy and mutual authentication.

公开(公告)号：US20200293288A1

公开(公告)日：2020-09-17

申请号：US16856887

申请日：2020-04-23

Applicant: STC.UNM

Inventor： James Plusquellic

IPC: G06F7/58 ,  G09C1/00 ,  H04L9/08 ,  H04L9/00

Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.

公开(公告)号：US20200235735A1

公开(公告)日：2020-07-23

申请号：US16843660

申请日：2020-04-08

Applicant: STC.UNM

Inventor： James Plusquellic ,  James Aarestad

IPC: H03K19/003 ,  H03K19/21 ,  H03K3/84 ,  H03K23/00 ,  H04L9/06 ,  H04L9/08

Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.

公开(公告)号：US20190089355A1

公开(公告)日：2019-03-21

申请号：US16185921

申请日：2018-11-09

Applicant: STC.UNM

Inventor： James Plusquellic ,  James Aarestad

IPC: H03K19/003 ,  H03K23/00 ,  H03K3/84 ,  H04L9/08 ,  H03K19/21 ,  H04L9/06

Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.

公开(公告)号：US20180349100A1

公开(公告)日：2018-12-06

申请号：US16051427

申请日：2018-07-31

Applicant: STC.UNM

Inventor： James Plusquellic

IPC: G06F7/58 ,  H04L9/08 ,  G09C1/00 ,  H04L9/00

CPC classification number: G06F7/588 ,  G06F2207/58 ,  G09C1/00 ,  H04L9/002 ,  H04L9/0866 ,  H04L2209/12 ,  H04L2209/26 ,  Y04S40/24

Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.

公开(公告)号：US10048939B2

公开(公告)日：2018-08-14

申请号：US14907423

申请日：2014-08-28

Applicant: STC.UNM

Inventor： James Plusquellic

IPC: G06F7/58 ,  G09C1/00 ,  H04L9/00 ,  H04L9/08

Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.

公开(公告)号：US11863304B2

公开(公告)日：2024-01-02

申请号：US16759729

申请日：2018-10-30

Applicant: STC.UNM

Inventor： James Plusquellic

IPC: H04L9/00 ,  H04L9/06 ,  H04L9/16

CPC classification number: H04L9/003 ,  H04L9/0631 ,  H04L9/16 ,  H04L2209/12

Abstract: A side-channel attack countermeasure that leverages implementation diversity and dynamic partial reconfiguration as mechanisms to reduce correlation in the power traces measured during a differential power analysis (DPA) attack. The technique changes the underlying hardware implementation of any encryption algorithm using dynamic partial reconfiguration (DPR) to resist side-channel-based attacks.