PACKAGED ELECTRONIC DEVICE COMPRISING A PLURALITY OF POWER TRANSISTORS

    公开(公告)号:US20230317685A1

    公开(公告)日:2023-10-05

    申请号:US18188918

    申请日:2023-03-23

    Abstract: Electronic device comprising at least a first and a second branch, each branch including a first and a second transistor arranged in series to each other and formed in respective dice of semiconductor material. The dice are sandwiched between a first substrate element and a second substrate element. The first and the second substrate elements are formed each by a multilayer including a first conductive layer, a second conductive layer and an insulating layer extending between the first and the second conductive layers. The first conductive layers of the first and the second substrate elements face towards the outside of the electronic device and define a first and a second main face of the electronic device. The second conductive layer of the first and the second substrate elements is shaped so as to form contact regions facing and in selective electrical contact with the plurality of dice.

    POWER SEMICONDUCTOR DEVICE WITH A DOUBLE ISLAND SURFACE MOUNT PACKAGE

    公开(公告)号:US20230282564A1

    公开(公告)日:2023-09-07

    申请号:US18306119

    申请日:2023-04-24

    CPC classification number: H01L23/49844 H01L23/3735 H01L23/49822

    Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

    PACKAGED SEMICONDUCTOR DEVICE HAVING IMPROVED RELIABILITY AND INSPECTIONABILITY AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20250087623A1

    公开(公告)日:2025-03-13

    申请号:US18956979

    申请日:2024-11-22

    Inventor: Agatino MINOTTI

    Abstract: Packaged device having a carrying base; an accommodation cavity in the carrying base; a semiconductor die in the accommodation cavity, the semiconductor die having die pads; a protective layer, covering the semiconductor die and the carrying base; first vias in the protective layer, at the die pads; and connection terminals of conductive material. The connection terminals have first connection portions in the first vias, in electrical contact with the die pads, and second connection portions, extending on the protective layer, along a side surface of the packaged device.

    CONNECTING STRIP FOR DISCRETE AND POWER ELECTRONIC DEVICES

    公开(公告)号:US20220320032A1

    公开(公告)日:2022-10-06

    申请号:US17701352

    申请日:2022-03-22

    Inventor: Agatino MINOTTI

    Abstract: A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.

    PACKAGED SEMICONDUCTOR DEVICE HAVING IMPROVED RELIABILITY AND INSPECTIONABILITY AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20220084980A1

    公开(公告)日:2022-03-17

    申请号:US17472207

    申请日:2021-09-10

    Inventor: Agatino MINOTTI

    Abstract: Packaged device having a carrying base; an accommodation cavity in the carrying base; a semiconductor die in the accommodation cavity, the semiconductor die having die pads; a protective layer, covering the semiconductor die and the carrying base; first vias in the protective layer, at the die pads; and connection terminals of conductive material. The connection terminals have first connection portions in the first vias, in electrical contact with the die pads, and second connection portions, extending on the protective layer, along a side surface of the packaged device.

    POWER SEMICONDUCTOR DEVICE WITH A DOUBLE ISLAND SURFACE MOUNT PACKAGE

    公开(公告)号:US20210159161A1

    公开(公告)日:2021-05-27

    申请号:US17142738

    申请日:2021-01-06

    Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

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