公开(公告)号：US20240038610A1

公开(公告)日：2024-02-01

申请号：US18355966

申请日：2023-07-20

Applicant: STMICROELECTRONICS (MALTA) LTD

Inventor： Roseanne DUCA

IPC: H01L23/29 ,  H01L23/053 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/296 ,  H01L23/053 ,  H01L24/48 ,  H01L25/0655 ,  H01L21/561 ,  H01L25/50 ,  H01L24/85 ,  H01L2224/48225 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73265 ,  H01L24/73 ,  H01L2224/85

Abstract: A method of manufacturing a semiconductor package with an one or more dice present within a transparent resin, which may be an epoxy-based transparent resin or a silicone-based transparent resin, includes coupling the one or more dice to respective surfaces of a plurality of base portions of a panel substrate. Each one of the respective surfaces is between ones of a plurality of walls of the panel substrate that protrude from the respective surfaces of the panel substrate. A plurality of wirebonds may be formed to provide electrical pathways between the one or more dice and conductive structures of the panel substrate accessible at the respective surfaces of the panel substrate. A transparent resin may be formed to fill recesses or cavities between ones of the plurality of walls, and the panel substrate may then be singulated along the plurality of walls.

公开(公告)号：US20210166949A1

公开(公告)日：2021-06-03

申请号：US17108471

申请日：2020-12-01

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Malta) Ltd

Inventor： Roseanne DUCA ,  Dario PACI ,  Pierpaolo RECANATINI

IPC: H01L21/324 ,  H01L23/16 ,  H01L23/31

Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.

公开(公告)号：US20230046645A1

公开(公告)日：2023-02-16

申请号：US17870235

申请日：2022-07-21

Applicant: STMicroelectronics (Malta) Ltd.

Inventor： Roseanne DUCA

IPC: H01L23/498 ,  H01L23/00 ,  B81B7/00

Abstract: A support substrate includes an insulating core layer, an electrically conductive layer over the insulating core layer and a solder mask layer over the electrically conductive layer. A back side of an integrated circuit chip is mounted to an upper surface of the support substrate at a die attach location. The upper surface of the support substrate includes a cavity located within the die attach location, where the cavity extends under the back side of the integrated circuit chip. The cavity is defined by an area where the solder mask layer and at least a portion of the electrically conductive layer have been removed. Bonding wires connect connection pads on a front side of the integrated circuit chip to connection pad on the upper surface of the support substrate.

公开(公告)号：US20230005755A1

公开(公告)日：2023-01-05

申请号：US17942843

申请日：2022-09-12

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (MALTA) Ltd

Inventor： Roseanne DUCA ,  Dario PACI ,  Pierpaolo RECANATINI

IPC: H01L21/324 ,  H01L23/16 ,  H01L23/31

Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.

公开(公告)号：US20190088562A1

公开(公告)日：2019-03-21

申请号：US16133065

申请日：2018-09-17

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Malta) Ltd

Inventor： Jerome LOPEZ ,  Roseanne DUCA

IPC: H01L23/10 ,  H01L23/498 ,  H01L21/50 ,  H01L23/31

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L23/3121 ,  H01L23/49838

Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.

公开(公告)号：US20240132340A1

公开(公告)日：2024-04-25

申请号：US17973084

申请日：2022-10-24

Applicant: STMicroelectronics (Malta) Ltd.

Inventor： Roseanne DUCA

IPC: B81B3/00 ,  B81C1/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/492 ,  H01L25/00 ,  H01L25/065

CPC classification number: B81B3/0072 ,  B81C1/00666 ,  H01L21/4875 ,  H01L23/4924 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/096 ,  B81C2203/038 ,  B81C2203/0771 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/167

Abstract: A sensor package includes a packaging formed by a package bottom, first and second sidewalls extending upwardly from first and second opposite sides of the package bottom, and third and fourth sidewalls extending upwardly from third and fourth opposite sides of the package bottom, the sidewalls and package bottom defining a cavity. An integrated circuit is attached to the package bottom. A plate extends between two of the sidewalls within the cavity and is spaced apart from the package bottom. Sensors are attached to a top surface of the plate on opposite sides of an opening. Wire bondings electrically connect pads on a top face of the sensor to corresponding pads on a top face of the integrated circuit, for example by passing through the opening in the plate or passing past a side end of the plate. A lid extends across and between the sidewalls to close the cavity.

公开(公告)号：US20200185288A1

公开(公告)日：2020-06-11

申请号：US16788627

申请日：2020-02-12

Applicant: STMicroelectroncis (Grenoble 2) SAS ,  STMicroelectronics (Malta) Ltd

Inventor： Jerome LOPEZ ,  Roseanne DUCA

IPC: H01L23/10 ,  H01L23/498 ,  H01L21/50 ,  H01L23/31

Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.