公开(公告)号：US5349214A

公开(公告)日：1994-09-20

申请号：US119554

申请日：1993-09-13

申请人： Saied N. Tehrani ,  X. Theodore Zhu ,  Herbert Goronkin ,  Jun Shen

发明人： Saied N. Tehrani ,  X. Theodore Zhu ,  Herbert Goronkin ,  Jun Shen

IPC分类号： H01L29/80 ,  H01L27/06 ,  H01L27/092 ,  H01L27/095 ,  H01L27/088 ,  H01L27/105 ,  H01L31/06

CPC分类号： H01L27/0605 ,  H01L27/092 ,  Y10S148/015 ,  Y10S148/072 ,  Y10S148/16

摘要： A heterojunction device including a first semiconductive layer on a substrate, a barrier layer on the first layer, a second semiconductive layer on the barrier layer and a multi-layer cap, on the second semiconductive layer. First and second gates positioned on layers of the cap to define first and second transistors, with the cap layers being selected and etched to pin the Fermi level in a first transistor conduction channel in the second semiconductive layer such that the number of carriers in the first conduction channel are substantially less than the number of carriers in surrounding portions of the second semiconductive layer and the Fermi level in a second transistor conduction channel in the first semiconductive layer such that the number of carriers in the second conduction channel are substantially less than the number of carriers in surrounding portions of the first semiconductive layer.

摘要翻译： 一种异质结装置，在第二半导体层上包括衬底上的第一半导体层，第一层上的阻挡层，阻挡层上的第二半导体层和多层帽。 位于盖的层上的第一和第二栅极限定第一和第二晶体管，其中盖层被选择和蚀刻以在第二半导体层中的第一晶体管导通通道中引导费米能级，使得第一和第二晶体管中的载流子数目 传导通道基本上小于第一半导体层中的第二半导体层的周围部分中的载流子数量和第二晶体管传导通道中的费米能级数，使得第二导电通道中的载流子数目基本上小于数量 在第一半导体层的周围部分的载体。

公开(公告)号：US5410160A

公开(公告)日：1995-04-25

申请号：US894963

申请日：1992-06-08

申请人： Herbert Goronkin ,  Jun Shen ,  Saied N. Tehrani ,  X. Theodore Zhu

发明人： Herbert Goronkin ,  Jun Shen ,  Saied N. Tehrani ,  X. Theodore Zhu

IPC分类号： H01L29/80 ,  H01L29/739 ,  H01L29/772 ,  H01L29/161 ,  H01L29/205 ,  H01L29/225

CPC分类号： H01L29/772 ,  H01L29/739

摘要： A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by barrier layers comprising wide bandgap material (18) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a P-type drain region (22b). Each channel is also coupled to an N-type source region (25b). With appropriate gate bias on a gate electrode (17), quantized energy levels in the channels (12, 14, 16) are aligned providing peak current flow by electrons tunneling from the conduction band of one or more N-channels (12, 16) to the valence band of the P-channel (14).

摘要翻译： 提供了具有由包括宽带隙材料（18）的阻挡层分开的多个垂直堆叠通道（12,14,16）的场效应半导体器件。 通道（12,14,16）形成在宽带隙缓冲层（11）上，每个通道耦合有P型漏极区域（22b）。 每个通道也耦合到N型源极区域（25b）。 在栅电极（17）上具有适当的栅极偏置，通道（12,14,16）中的量化能级对齐，从一个或多个N沟道（12,16）的导带隧穿的电子提供峰值电流， 到P沟道（14）的价带。

公开(公告)号：US5298441A

公开(公告)日：1994-03-29

申请号：US709741

申请日：1991-06-03

申请人： Herbert Goronkin ,  Jun Shen ,  Saied N. Tehrani ,  X. Theodore Zhu

发明人： Herbert Goronkin ,  Jun Shen ,  Saied N. Tehrani ,  X. Theodore Zhu

IPC分类号： H01L29/772 ,  H01L21/265

CPC分类号： H01L29/7725 ,  Y10S148/097

摘要： A high transconductance HFET (21) utilizes nonalloy semiconductor materials (26) to form a strained channel layer (26) that has a deep quantum well (38). The materials utilized for layers adjacent to the channel layer (26) apply strain to the channel layer (26) and create an excess of high mobility carriers in the channel layer (26). The materials also form a deep quantum well (38) that confines the high mobility carriers to the channel (26). The high mobility carriers and the high confinement provide an HFET (21) that has high transconductance, high frequency response, and sharp pinch-off characteristics.

摘要翻译： 高跨导HFET（21）利用非合金半导体材料（26）形成具有深量子阱（38）的应变通道层（26）。 用于与沟道层（26）相邻的层的材料对沟道层（26）施加应变，并在沟道层（26）中产生过量的高迁移率载流子。 这些材料还形成将高迁移率载流子限制到通道（26）的深量子阱（38）。 高迁移率载流子和高限制性提供了具有高跨导，高频响应和清晰夹断特性的HFET（21）。

公开(公告)号：US5049951A

公开(公告)日：1991-09-17

申请号：US630613

申请日：1990-12-20

申请人： Herbert Goronkin ,  Saied N. Tehrani ,  X. Theodore Zhu

发明人： Herbert Goronkin ,  Saied N. Tehrani ,  X. Theodore Zhu

IPC分类号： H01L21/203 ,  H01L21/338 ,  H01L29/10 ,  H01L29/12 ,  H01L29/15 ,  H01L29/205 ,  H01L29/778 ,  H01L29/812

CPC分类号： B82Y10/00 ,  H01L29/1075 ,  H01L29/122 ,  H01L29/155 ,  H01L29/7782

摘要： A heterojunction field effect transistor (HFET) having a source, drain, and channel, wherein the channel is a top layer of a superlattice buffer, eliminating the need for a thick buffer layer. The superlattice buffer comprises alternating barrier and quantum well layers which are thin enough to provide wide separation in energy bands within the quantum wells. In a preferred embodiment the channel comprises a quantum well and one to five monolayers having a different bandgap than the channel region and serves to modify electron wave function and conduction band energy in the channel region. Preferably, a ten period AlAs/GaAs superlattice is formed underneath the channel.

摘要翻译： 具有源极，漏极和沟道的异质结场效应晶体管（HFET），其中该沟道是超晶格缓冲器的顶层，消除了对厚缓冲层的需要。 超晶格缓冲器包括交替的势垒和量子阱层，它们足够薄以在量子阱内的能带中提供宽的分离。 在优选实施例中，该通道包括量子阱和一至五个具有与沟道区不同的带隙的单层，并且用于修改沟道区中的电子波函数和导带能量。 优选地，在通道下方形成十个周期的AlAs / GaAs超晶格。

公开(公告)号：US5289014A

公开(公告)日：1994-02-22

申请号：US930958

申请日：1992-08-17

申请人： Herbert Goronkin ,  Jun Shen ,  Saied Tehrani ,  X. Theodore Zhu

发明人： Herbert Goronkin ,  Jun Shen ,  Saied Tehrani ,  X. Theodore Zhu

IPC分类号： H01L21/20 ,  H01L29/06 ,  H01L29/76 ,  H01L29/80 ,  H01L29/161 ,  H01L29/205

CPC分类号： B82Y10/00 ,  H01L29/7613

摘要： A semiconductor device having a vertical interconnect or via stacked formed by quantum well comprising a semiconductor material is provided. A first semiconductor device (11) having a current carrying region (19) is formed in a first horizontal plane. A second semiconductor device (12) having a current carrying region (29) is formed in a second horizontal plane. Each of the current carrying regions have a first quantized energy level that is substantially equal. A semiconductor via (31) couples the current carrying region (19) of the first semiconductor device (11) to the current carrying region (29) of the second device (12), wherein the semiconductor via (31) has a first quantized energy level capable of alignment with the quantized energy levels of the current carrying regions (19, 29) of the first and second semiconductor devices (11,12).

摘要翻译： 提供了具有由包括半导体材料的量子阱形成的垂直互连或通过层叠形成的半导体器件。 具有载流区域（19）的第一半导体器件（11）形成在第一水平面中。 具有载流区域（29）的第二半导体器件（12）形成在第二水平面中。 每个电流承载区域具有基本相等的第一量化能级。 半导体通孔（31）将第一半导体器件（11）的载流区域（19）耦合到第二器件（12）的载流区域（29），其中半导体通孔（31）具有第一量子化能 能够与第一和第二半导体器件（11,12）的载流区域（19,29）的量化能级对准。

公开(公告)号：US5221849A

公开(公告)日：1993-06-22

申请号：US899439

申请日：1992-06-16

申请人： Herbert Goronkin ,  Jun Shen ,  Saied Tehrani ,  X. Theodore Zhu

发明人： Herbert Goronkin ,  Jun Shen ,  Saied Tehrani ,  X. Theodore Zhu

IPC分类号： H01L29/80 ,  H01L27/06 ,  H01L29/10 ,  H01L29/772

CPC分类号： H01L27/0605 ,  H01L29/1029 ,  H01L29/772

摘要： A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by independent gate electrodes (13, 15) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a drain electrode (21). Each channel is also coupled to a source electrode (25-26). The quantum well channels (12, 14, 16) and quantum well gates (13, 15) are separated from each other by barrier layers (18) of a wide bandgap semiconductor material.

摘要翻译： 提供具有由独立的栅电极（13,15）分离的多个垂直堆叠的通道（12,14,16）的场效半导体器件。 通道（12,14,16）形成在宽带隙缓冲层（11）上，每个通道与漏电极（21）相连。 每个通道也耦合到源电极（25-26）。 量子阱通道（12,14,16）和量子阱栅极（13,15）通过宽带隙半导体材料的阻挡层（18）彼此分离。

公开(公告)号：US5280180A

公开(公告)日：1994-01-18

申请号：US932116

申请日：1992-08-19

申请人： Herbert Goronkin ,  Jun Shen ,  Saied Tehrani ,  Raymond K. Tsui ,  X. Theodore Zhu

发明人： Herbert Goronkin ,  Jun Shen ,  Saied Tehrani ,  Raymond K. Tsui ,  X. Theodore Zhu

IPC分类号： H01L21/20 ,  H01L23/535 ,  H01L29/06 ,  H01L29/80 ,  H01L29/161 ,  H01L29/205

CPC分类号： H01L23/535 ,  H01L2924/0002

摘要： A semiconductor device having a lateral interconnect or via formed by quantum well comprising a semiconductor material is provided. The lateral interconnect (17, 18, 19) formed by a quantum well comprising a first semiconductor material composition. A first semiconductor region (11, 12, 13) comprising a second material type is formed adjacent to the lateral interconnect (17, 18, 19). A second semiconductor region (23, 24, 26) comprising the second material type is adjacent to the lateral interconnect (17, 18, 19) so that the lateral interconnect (17, 18, 19) separates the first (11, 12, 13) and second (23, 24, 26) semiconductor regions. The first (17, 18, 19) and second (23, 24, 26) semiconductor regions have a first quantized energy level that is substantially equal. The lateral interconnect (17, 18, 19) has a first quantized energy level capable of alignment with the quantized energy levels of the first (11, 12, 13) and second (23, 24, 26) semiconductor regions.

摘要翻译： 提供了具有由包括半导体材料的量子阱形成的横向互连或通孔的半导体器件。 由包括第一半导体材料组合物的量子阱形成的横向互连（17,18,19）。 包括第二材料类型的第一半导体区域（11,12,13）形成为与横向互连（17,18,19）相邻。 包括第二材料类型的第二半导体区域（23,24,26）与横向互连（17,18,19）相邻，使得横向互连（17,18,19）将第一（11,12,13） ）和第二（23,24,26）个半导体区域。 第一（17,18,19）和第二（23,24,26）半导体区域具有基本相等的第一量化能级。 横向互连（17,18,19）具有能够与第一（11,12,13）和第二（23,24,26）半导体区域的量化能级对准的第一量化能级。

公开(公告)号：US6153443A

公开(公告)日：2000-11-28

申请号：US216821

申请日：1998-12-21

申请人： Mark Durlam ,  Gloria Kerszykowski ,  Jon M. Slaughter ,  Eugene Chen ,  Saied N. Tehrani ,  Kelly W. Kyler ,  X. Theodore Zhu

发明人： Mark Durlam ,  Gloria Kerszykowski ,  Jon M. Slaughter ,  Eugene Chen ,  Saied N. Tehrani ,  Kelly W. Kyler ,  X. Theodore Zhu

IPC分类号： G11C11/14 ,  G11C11/15 ,  H01F10/14 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/22 ,  H01L43/08 ,  H01L21/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/115

摘要： An improved and novel fabrication method for magnetoresistive random access memory (MRAM) is provided. An MRAM device has memory elements and circuitry for managing the memory elements. The circuitry includes transistor (12a), digit line (29), etc., which are integrated on a substrate (11). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (53, 54). A dielectric layer (40, 41) is deposited on the circuit, and trenches (42, 43) are formed in the dielectric layer. A blanket layer (46), which includes magnetic layers (48, 49) and a non-magnetic layer (50) sandwiched by the magnetic layers, is deposited on dielectric layer (41) and in the trenches. Then, the blanket layer outside the trenches is removed and MRAM elements (53, 54) are formed in the trenches.

摘要翻译： 提供了一种用于磁阻随机存取存储器（MRAM）的改进和新颖的制造方法。 MRAM设备具有用于管理存储器元件的存储器元件和电路。 电路包括集成在基板（11）上的晶体管（12a），数字线（29）等。 首先在CMOS工艺之下制造电路，然后制造磁存储元件（53,54）。 电介质层（40,41）沉积在电路上，并在电介质层中形成沟槽（42,43）。 包含磁性层（48,49）和由磁性层夹着的非磁性层（50）的覆盖层（46）沉积在电介质层（41）和沟槽中。 然后，去除沟槽外的覆盖层，并在沟槽中形成MRAM元件（53,54）。

公开(公告)号：US5142349A

公开(公告)日：1992-08-25

申请号：US724077

申请日：1991-07-01

申请人： X. Theodore Zhu ,  Jonathan K. Abrokwah ,  Herbert Goronkin ,  William J. Ooms ,  Carl L. Shurboff

发明人： X. Theodore Zhu ,  Jonathan K. Abrokwah ,  Herbert Goronkin ,  William J. Ooms ,  Carl L. Shurboff

IPC分类号： H01L21/338 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L27/095 ,  H01L29/10 ,  H01L29/20 ,  H01L29/778 ,  H01L29/80 ,  H01L29/812

CPC分类号： H01L27/0605 ,  H01L27/0922 ,  H01L29/1029 ,  H01L29/802

摘要： A heterojunction field effect transistor structure having a plurality of vertically stacked field effect devices. Two or more devices having electrically independent source and drain regions are formed such that a single gate electrode controls current flow in each of the devices. Each of the vertically stacked FETs have electrically isolated channel regions which may be controlled by a single gate electrode. Vertically stacked devices provide greater device packing density.

公开(公告)号：US5243206A

公开(公告)日：1993-09-07

申请号：US724636

申请日：1991-07-02

申请人： X. Theodore Zhu ,  Jonathan K. Abrokwah ,  Herbert Goronkin ,  William J. Ooms ,  Carl L. Shurboff

发明人： X. Theodore Zhu ,  Jonathan K. Abrokwah ,  Herbert Goronkin ,  William J. Ooms ,  Carl L. Shurboff

IPC分类号： H01L21/8232 ,  H01L27/06 ,  H01L27/11 ,  H03K19/08

CPC分类号： H01L27/11 ,  H01L27/0605 ,  Y10S257/903

摘要： Logic circuits using a heterojunction field effect transistor structure having vertically stacked complementary devices is provided. A P-channel quantum well and an N-channel quantum well are formed near each other under a single gate electrode and separated from each other by a thin layer of barrier material. P-source and P-drain regions couple to the P-channel. N-source and N-drain regions couple to the N-channel. The P-source/drain regions are electrically isolated from the N-source/drain regions so the P-channel and N-channel devices may be interconnected to provide many logic functions.