公开(公告)号：US20160204125A1

公开(公告)日：2016-07-14

申请号：US14799995

申请日：2015-07-15

Applicant: Samsung Display Co., Ltd.

Inventor： Yung Bin CHUNG ,  Chul-Hyun BAEK ,  Eun Jeong CHO ,  Jung Yun JO

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/0217 ,  H01L27/1248 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78606 ,  H01L29/78669 ,  H01L29/78678

Abstract: A thin-film transistor array panel includes an insulation substrate, a gate line disposed on the insulation substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line disposed on the semiconductor layer and including a source electrode, a drain electrode disposed on the semiconductor layer and facing the source electrode, a first electrode disposed on the gate insulating layer, a first passivation layer disposed on the first electrode and including silicon nitride, a second passivation layer disposed on the first passivation and including silicon nitride, and a second electrode disposed on the passivation layer, in which a first ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the first passivation layer is different from a second ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the second passivation layer.

Abstract translation: 薄膜晶体管阵列面板包括绝缘基板，设置在绝缘基板上的栅极线，设置在栅极线上的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线，以及 包括源电极，设置在半导体层上并面对源电极的漏电极，设置在栅绝缘层上的第一电极，设置在第一电极上并包括氮化硅的第一钝化层，设置在第一电极上的第二钝化层 第一钝化并且包括氮化硅，以及设置在钝化层上的第二电极，其中第一钝化层中氮 - 氢键与硅 - 氢键的第一比例不同于氮 - 氢键与硅的第二比率 在第二钝化层中的氢键。

公开(公告)号：US20170207343A1

公开(公告)日：2017-07-20

申请号：US15480102

申请日：2017-04-05

Applicant: Samsung Display Co., Ltd.

Inventor： Seung Ho JUNG ,  Chaun Gi CHOI ,  Hye Young PARK ,  Eun Young LEE ,  Joo Hee JEON ,  Eun Jeong CHO ,  Bo Geon JEON ,  Yung Bin CHUNG

IPC: H01L29/786 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L29/78603 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/3244 ,  H01L27/3262 ,  H01L29/7849 ,  H01L29/78633 ,  H01L29/7869 ,  H01L51/0097 ,  H01L51/5256 ,  H01L2251/5338 ,  H01L2251/55 ,  Y02E10/549

Abstract: A thin film transistor array panel device comprises: a base substrate; a barrier layer disposed over the base substrate and comprising a plurality of transparent material layers; and an array of thin film transistors disposed over the barrier layer. A difference between a refractive index of the barrier layer and a refractive index of the base substrate may be within about 6%. The transparent material layers may be arranged such that the transparent material layers having compressive residual stress and the transparent material layers having tensile residual stress are alternately stacked. Each of the transparent material layers may comprise silicon oxynitride (SiON).

公开(公告)号：US20160197197A1

公开(公告)日：2016-07-07

申请号：US14879993

申请日：2015-10-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jung Yun JO ,  Ki Seong SEO ,  Eun Jeong CHO

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1222 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02686 ,  H01L29/66757 ,  H01L29/78675

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: an insulating substrate; a polycrystal semiconductor layer formed on the insulating substrate; a buffer layer formed below the polycrystal semiconductor layer and containing fluorine; a gate electrode overlapping the polycrystal semiconductor layer; a source electrode and a drain electrode overlapping the polycrystal semiconductor layer and separated from each other; and a pixel electrode electrically connected to the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：绝缘基板; 形成在所述绝缘基板上的多晶半导体层; 形成在多晶半导体层下面并含有氟的缓冲层; 与多晶半导体层重叠的栅电极; 源电极和漏电极，与多晶半导体层重叠并分离; 以及电连接到漏电极的像素电极。

公开(公告)号：US20170170209A1

公开(公告)日：2017-06-15

申请号：US15445650

申请日：2017-02-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Yun JO ,  Ki Seong SEO ,  Eun Jeong CHO

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1222 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02686 ,  H01L29/66757 ,  H01L29/78675

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: an insulating substrate; a polycrystal semiconductor layer formed on the insulating substrate; a buffer layer formed below the polycrystal semiconductor layer and containing fluorine; a gate electrode overlapping the polycrystal semiconductor layer; a source electrode and a drain electrode overlapping the polycrystal semiconductor layer and separated from each other; and a pixel electrode electrically connected to the drain electrode.

公开(公告)号：US20170110481A1

公开(公告)日：2017-04-20

申请号：US15130654

申请日：2016-04-15

Applicant: Samsung Display Co., Ltd.

Inventor： Yung Bin CHUNG ,  Bo Geon JEON ,  Eun Jeong CHO ,  Tae Young AHN ,  Woo Seok JEON ,  Sung Hoon YANG

IPC: H01L27/12 ,  G02F1/1362 ,  H01L29/786 ,  H01L21/4763 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/465 ,  G02F1/1368 ,  H01L29/45

CPC classification number: H01L27/1222 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/465 ,  H01L21/47635 ,  H01L27/1262 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/78606

Abstract: Provided are liquid crystal display and the method for manufacturing the same. According to an aspect of the present invention, there is provided a liquid crystal display device, including a first substrate; a gate electrode disposed on the first substrate; a semiconductor pattern layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the semiconductor pattern layer and facing each other, wherein a diffusion prevention pattern is disposed on the semiconductor pattern layer to prevent diffusion into the semiconductor pattern layer or to maintain uniform thickness of the semiconductor pattern layer.

公开(公告)号：US20160322602A1

公开(公告)日：2016-11-03

申请号：US15045688

申请日：2016-02-17

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Seung Ho JUNG ,  Chaun Gi CHOI ,  Hye Young PARK ,  Eun Young LEE ,  Joo Hee JEON ,  Eun Jeong CHO ,  Bo Geon JEON ,  Yung Bin CHUNG

IPC: H01L51/52 ,  H01L51/00

CPC classification number: H01L29/78603 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/3244 ,  H01L27/3262 ,  H01L29/7849 ,  H01L29/78633 ,  H01L29/7869 ,  H01L51/0097 ,  H01L51/5256 ,  H01L2251/5338 ,  H01L2251/55 ,  Y02E10/549

Abstract: A thin film transistor array panel device comprises: a base substrate; a barrier layer disposed over the base substrate and comprising a plurality of transparent material layers; and an array of thin film transistors disposed over the barrier layer. A difference between a refractive index of the barrier layer and a refractive index of the base substrate may be within about 6%. The transparent material layers may be arranged such that the transparent material layers having compressive residual stress and the transparent material layers having tensile residual stress are alternately stacked. Each of the transparent material layers may comprise silicon oxynitride (SiON).

Abstract translation: 薄膜晶体管阵列面板装置包括：基底; 阻挡层，设置在所述基底基板上并且包括多个透明材料层; 以及设置在阻挡层上的薄膜晶体管阵列。 阻挡层的折射率与基底的折射率之差可以在约6％以内。 透明材料层可以布置成使得具有压缩残余应力的透明材料层和具有拉伸残余应力的透明材料层交替堆叠。 每个透明材料层可以包括氮氧化硅（SiON）。