Abstract:
A display device and a method of manufacturing the same are provided. The display device, comprises a first base substrate, a first barrier layer disposed on the first base substrate, a second base substrate disposed on the first barrier layer, at least one transistor disposed on the second base substrate, and an organic light emitting diode disposed on the at least one transistor, wherein the first barrier layer includes a silicon oxide, and has an adhesion force of 200 gf/inch or more to the second base substrate.
Abstract:
An exemplary embodiment of the described technology relates generally to a display apparatus including a plurality of pixels and corresponding to one area of a substrate for displaying an image, and a pad area corresponding to another area of the substrate, the pad area including a lower electrode configured to transmit an electric signal to the pixels, and a plurality of pad electrodes electrically connecting the lower electrode and a driving chip, wherein each of the pad electrodes includes a first contact surface for contacting the lower electrode, a second contact surface for contacting the driving chip, and an oxide layer on a surface of the pad electrode that is exposed to the outside, and that connects the first contact surface and the second contact surface.
Abstract:
There is provided a method of manufacturing an oxide thin film transistor (TFT). The method includes forming a gate electrode on a substrate, forming a gale insulating layer on the gate electrode, forming an oxide semiconductor layer including a channel layer on the gate insulating layer, forming a source electrode and a drain electrode separated from each other on the oxide semiconductor layer, first plasma processing the substrate on which the source electrode and the drain electrode are formed at a carbon (C) atmosphere, secondly plasma processing the substrate al a nitrogen oxide atmosphere, and sequentially forming a first protective layer and a second protective layer on the substrate.
Abstract:
A display device includes a buffer layer disposed on a substrate and comprising a first buffer film, and a second buffer film, wherein the first buffer film and the second buffer film are sequentially stacked in a thickness direction of the display device; a semiconductor pattern disposed on the buffer layer; a gate insulating layer disposed on the semiconductor pattern; and a gate electrode disposed on the gate insulating layer, wherein the first buffer film and the second buffer film comprise a same material, and a density of the first buffer film is greater than a density of the second buffer film.
Abstract:
An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.
Abstract:
A liquid crystal display device includes a substrate; a gate line and a data line positioned on the substrate; a thin film transistor connected to the gate line and the data line; a passivation layer positioned on the gate line, the data line, and the thin film transistor; a first electrode positioned on the passivation layer; an interlayer insulating layer positioned on the first electrode; and a second electrode positioned on the interlayer insulating layer, wherein the first electrode includes a first layer made of an indium-zinc oxide in which a weight ratio of an indium oxide is 20 wt % or less or made of a transparent metal oxide that does not contain an indium oxide.
Abstract:
A display device includes a substrate including pixels; a buffer layer disposed on the substrate; an etch stopper layer disposed between the substrate and the buffer layer; and at least one penetrating-hole penetrating the substrate, the buffer layer, and the etch stopper layer, wherein the etch stopper layer includes amorphous carbon.
Abstract:
A display device includes: a substrate; a pad portion in a non-display area of the substrate and including a plurality of pads; a driver arranged at the pad portion to contact the pads; an interlayer insulating layer on the substrate; and an auxiliary layer in the non-display area, and each of the pads includes a first pad electrode, a second pad electrode, and a third pad electrode, which are sequentially arranged on the substrate, a width of the third pad electrode is greater than a width of the second pad electrode and a width of the first pad electrode, and a thickness of the auxiliary layer between the third pad electrode and the interlayer insulating layer is thicker than a thickness of the auxiliary layer between the third pad electrode and the second pad electrode.
Abstract:
A display device includes: a flexible substrate having a display area for displaying an image and a peripheral area outside the display area; a first pad electrode in the peripheral area of the flexible substrate; and a driver connected to the first pad electrode. The driver includes: a circuit board including a driving circuit; a second pad electrode on one side of the circuit board and facing the first pad electrode; a convex structure on one side of the second pad electrode and having an oval cross-section; and a bump electrode on one side of the convex structure and connected to the first pad electrode. The bump electrode includes a column covering the convex structure and a convex portion extending from one side of the column and protruding to the first pad electrode.
Abstract:
A thin film transistor array panel and method of manufacturing. The thin film transistor array panel includes a substrate, a first gate electrode positioned on the substrate, a gate insulating layer positioned on the first gate, an oxide semiconductor positioned on the gate insulating layer and including a channel region, at least one etch stopper positioned on the oxide semiconductor, a second gate electrode, a source electrode and a drain electrode positioned on the at least one etch stopper, a passivation layer formed on the second gate electrode, the source electrode and the drain electrode; and a pixel electrode positioned on the passivation layer and connected to the drain electrode, in which the oxide semiconductor includes an N+ region formed in a portion exposed through the at least one etch stopper.