Abstract:
Embodiments of the invention provide an electronic component-embedded substrate and a manufacturing method thereof. According to at least one embodiment, the electronic component-embedded substrate includes a cavity formed in a core substrate and including two or more embedding spaces which have a rectangular shape (when viewed on a plane) and are connected to each other by a connecting space, and two or more electronic components separately accommodated in the embedding spaces of the cavity, respectively. According to at least one embodiment, neighboring long sides of first and second embedding spaces are partially connected to each other by the connecting space, and one side (when viewed on the plane) forming a connecting width of the connecting space connecting the first and second embedding spaces to each other coincides with one short side of the first embedding space, and the other side (when viewed on the plane) coincides with the other short side of the second embedding space.
Abstract:
Disclosed herein are a method for manufacturing an electronic component embedding substrate and an electronic component embedding substrate. The method for manufacturing an electronic component embedding substrate includes: inserting an electronic component into a cavity formed in a core substrate; stacking a first insulating layer on one side of the core substrate into which the electronic component is inserted; performing surface treatment on the other side of the core substrate opposite to a direction in which the first insulating layer is stacked to improve a surface roughness of at least an exposed surface of the first insulating layer; and stacking a second insulating layer on the other side of the core substrate so as to be bonded to the exposed surface of the first insulating layer of which the surface roughness is improved. In addition, disclosed herein is the electronic component embedding substrate.
Abstract:
A fan-out semiconductor package includes a redistribution layer, an interconnection member, a semiconductor chip, and a protective layer. The interconnection member has a through hole disposed on the redistribution layer. The semiconductor chip is disposed on the redistribution layer exposed within the through hole. The protective layer is formed between the redistribution layer and the interconnection member, and coupled to the interconnection member to protect the interconnection member.
Abstract:
Disclosed herein are a method for manufacturing an electronic component embedding substrate and an electronic component embedding substrate. The method for manufacturing an electronic component embedding substrate includes: inserting an electronic component into a cavity formed in a core substrate; stacking a first insulating layer on one side of the core substrate into which the electronic component is inserted; performing surface treatment on the other side of the core substrate opposite to a direction in which the first insulating layer is stacked to improve a surface roughness of at least an exposed surface of the first insulating layer; and stacking a second insulating layer on the other side of the core substrate so as to be bonded to the exposed surface of the first insulating layer of which the surface roughness is improved. In addition, disclosed herein is the electronic component embedding substrate.
Abstract:
Embodiments of the invention provide a method of manufacturing an electronic component-embedded printed circuit board. The method includes the steps of providing a base plate, which has a cavity formed in a thickness direction thereof and to one side of which tape is adhered, and disposing an electronic component in the cavity, such that an active surface of the electronic component is flush with one side of the base plate. The method further includes forming an insulating material layer on the other side of the base plate to bury the electronic component, and removing the tape from the one side of the base plate and then forming a first circuit layer including connection patterns coming into contact with connecting terminals of the electronic component on the one side of the base plate.
Abstract:
Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized