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    EXTREME ULTRAVIOLET (EUV) PHOTOMASK
    1.
    发明公开
    EXTREME ULTRAVIOLET (EUV) PHOTOMASK 审中-公开

    公开(公告)号：US20230400758A1

    公开(公告)日：2023-12-14

    申请号：US18317328

    申请日：2023-05-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yigwon KIM ,  Sangjin KIM ,  Jihun LEE ,  Jinhee JANG ,  Jeonghyun KIM

    IPC: G03F1/22

    CPC classification number: G03F1/22

    Abstract: An extreme ultraviolet (EUV) photomask may include a mask structure including a main region, a scribe lane region surrounding the main region, buffer regions outside the scribe lane region and apart from each other and each having a same first width, and a black border region outside the buffer regions. The buffer regions may include a first buffer region, a second buffer region, and a third buffer region. The black border region may include a first corner region, a second corner region, and a third corner region. The first corner region may contact the first buffer region and the second buffer region. The second corner region may contact the first buffer region, the third buffer region, and a side of the scribe lane region. The third corner region may contact the second buffer region and the third buffer region.

    SEMICONDUCTOR DEVICE
    5.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240349483A1

    公开(公告)日：2024-10-17

    申请号：US18415754

    申请日：2024-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SOHYUN PARK ,  Inwoo KIM ,  Sangho LEE ,  Jihun LEE

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

    Abstract: A semiconductor device includes an active pattern on a substrate; a bit line structure on a central portion of the active pattern; a first spacer structure and a second spacer structure disposed on a first sidewall and a second sidewall, respectively, of the bit line structure, the first sidewall and the second sidewall of the bit line structure facing each other in the first direction; a lower contact plug on each of opposite end portions of the active pattern; and an upper contact plug on the lower contact plug. The upper contact plug may include a conductive pattern; and a conductive spacer covering a lower surface of the conductive pattern, wherein the conductive spacer contacts an outer sidewall of the first spacer structure, and does not contact an outer sidewall of the second spacer structure.

    ELECTRONIC DEVICE FOR DISPLAYING PLURALITY OF APPLICATION EXECUTION SCREENS, AND METHOD RELATED THERETO
    6.
    发明公开
    ELECTRONIC DEVICE FOR DISPLAYING PLURALITY OF APPLICATION EXECUTION SCREENS, AND METHOD RELATED THERETO 审中-公开

    公开(公告)号：US20230205555A1

    公开(公告)日：2023-06-29

    申请号：US18116654

    申请日：2023-03-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinyung JUNG ,  Jihun LEE ,  Jaemin JUNG ,  Younghak OH

    IPC: G06F9/451 ,  G06F3/0482 ,  G06F1/16

    CPC classification number: G06F9/451 ,  G06F3/0482 ,  G06F1/1677

    Abstract: An electronic device includes: a foldable display; a processor operationally coupled with the display; and a memory operationally coupled with the processor, wherein the memory stores instructions that, when executed, cause the processor to: detect a screen layout state of the foldable display based on at least one of a folding angle of the foldable display, a rotation angle of the foldable display, a mounting state of the electronic device, or a gripped state of the electronic device; determine a plurality of applications for execution, based on the detected screen layout state; determine a plurality of regions of the foldable display on which the plurality of applications are to be displayed, based on the detected screen layout state; and display execution screens of the plurality of applications on the plurality of regions.

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230320076A1

    公开(公告)日：2023-10-05

    申请号：US17983489

    申请日：2022-11-09

    Applicant: Samsung Electronics Co., LTD.

    Inventor： HYO-SUB KIM ,  Kseok LEE ,  Myeong-Dong LEE ,  Jongmin KIM ,  Hui-Jung KIM ,  Jihun LEE ,  Hongjun LEE

    IPC: H01L27/108 ,  G11C5/06

    CPC classification number: H01L27/10814 ,  G11C5/063

    Abstract: A semiconductor memory device includes: a device isolation pattern provided on a substrate to provide a first active portion and a second active portion; a first storage node pad disposed on the first active portion; a second storage node pad disposed on the second active portion; a pad separation pattern disposed between the first and second storage node pads; a word line disposed in the substrate to cross the first and second active portions; a bit line disposed on the pad separation pattern and crossing the word line; a buffer layer disposed on the pad separation pattern; and a mask polysilicon pattern interposed between the buffer layer and the bit line, wherein a side surface of the mask polysilicon pattern is substantially aligned to a side surface of the bit line, and the mask polysilicon pattern is vertically overlapped with the pad separation pattern.

    METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220199473A1

    公开(公告)日：2022-06-23

    申请号：US17386323

    申请日：2021-07-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seongkeun CHO ,  Eunhee JEANG ,  Jihun LEE ,  Gyumin JEONG ,  Hyunjae KANG ,  Taemin EARMME

    IPC: H01L21/66 ,  H01L21/311

    Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming a parent pattern, forming an upper thin film on the parent pattern, forming a child pattern on the upper thin film, measuring a diffraction light from the parent and child patterns to obtain an intensity difference curve of the diffraction light versus its wavelength, and performing an overlay measurement process on the parent and child patterns using the diffraction light, which has the same wavelength as a peak of the intensity difference curve located near a peak of reflectance of the parent and child patterns, to obtain an overlay measurement value.

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