公开(公告)号：US10050041B1

公开(公告)日：2018-08-14

申请号：US15954744

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Sic Yoon ,  Ho-In Ryu ,  Ki-Seok Lee ,  Chang-Hyun Cho

IPC: H01L27/108 ,  H01L29/423 ,  H01L21/761 ,  H01L21/311

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.

公开(公告)号：US20190378590A1

公开(公告)日：2019-12-12

申请号：US16244890

申请日：2019-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-HO JOO ,  Gyu-Yeol Kim ,  Jae-Young Lee ,  Chang-Hyun Cho

IPC: G11C29/56 ,  G11C29/10 ,  G01R31/3183 ,  G01R31/317

Abstract: A test interface board includes one or more relay circuits and a synchronization signal generator. The relay circuits duplicate a test signal from an automated test equipment (ATE), apply duplicated test signals to each of a plurality of devices under test (DUTs) through one of corresponding channels, and provide the ATE with a plurality of test result signals received from each of the DUTs in response to the duplicated test signals. The synchronization signal generator receives a plurality of status signals from each of the DUTs and provides a timing synchronization signal to the ATE. Each of the status signals indicates a completion of a test operation in one of the DUTs, the test operation is associated with the test signal, and the synchronization signal generator activates the timing synchronization signal when all of the status signals indicate the completion of the test operation.

公开(公告)号：US09899487B2

公开(公告)日：2018-02-20

申请号：US15404703

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong Lee ,  Hye-Young Kang ,  Young-Sin Kim ,  Yong-Kwan Kim ,  Byoung-Wook Jang ,  Augustin Jinwoo Hong ,  Dong-Sik Kong ,  Chang-Hyun Cho

IPC: H01L27/148 ,  H01L29/80 ,  H01L29/76 ,  H01L29/94 ,  H01L21/336 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.

公开(公告)号：US20170263723A1

公开(公告)日：2017-09-14

申请号：US15404703

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong LEE ,  Hye-Young Kang ,  Young-Sin Kim ,  Yong-Kwan Kim ,  Byoung-Wook Jang ,  Augustin Jinwoo Hong ,  Dong-Sik Kong ,  Chang-Hyun Cho

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.

公开(公告)号：US09177891B2

公开(公告)日：2015-11-03

申请号：US14045648

申请日：2013-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-Nam Kim ,  Sun-Young Park ,  Soo-Ho Shin ,  Kye-Hee Yeom ,  Hyeon-Woo Jang ,  Jin-Won Jeong ,  Chang-Hyun Cho ,  Hyeong-Sun Hong

IPC: H01L23/52 ,  H01L23/48 ,  H01L27/108

CPC classification number: H01L27/0207 ,  H01L23/48 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

Abstract translation: 半导体器件包括与衬底上的有源区相交并沿第一方向延伸的多个位线，形成在相邻位线之间的有源区上的接触焊盘和设置在多个位的侧壁上的多个间隔件 线条。 接触垫的上部插入在相邻间隔件之间，并且接触垫的下部具有大于相邻间隔件之间的距离的宽度。

公开(公告)号：US09536868B2

公开(公告)日：2017-01-03

申请号：US14875385

申请日：2015-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-Nam Kim ,  Sun-Young Park ,  Soo-Ho Shin ,  Kye-Hee Yeom ,  Hyeon-Woo Jang ,  Jin-Won Jeong ,  Chang-Hyun Cho ,  Hyeong-Sun Hong

IPC: H01L23/48 ,  H01L27/02 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

CPC classification number: H01L27/0207 ,  H01L23/48 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

Abstract translation: 半导体器件包括与衬底上的有源区相交并沿第一方向延伸的多个位线，形成在相邻位线之间的有源区上的接触焊盘和设置在多个位的侧壁上的多个间隔件 线条。 接触垫的上部插入在相邻间隔件之间，并且接触垫的下部具有大于相邻间隔件之间的距离的宽度。

公开(公告)号：US10811118B2

公开(公告)日：2020-10-20

申请号：US16244890

申请日：2019-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho Joo ,  Gyu-Yeol Kim ,  Jae-Young Lee ,  Chang-Hyun Cho

IPC: G01R31/3183 ,  G11C29/56 ,  G01R31/317 ,  G11C29/10

Abstract: A test interface board includes one or more relay circuits and a synchronization signal generator. The relay circuits duplicate a test signal from an automated test equipment (ATE), apply duplicated test signals to each of a plurality of devices under test (DUTs) through one of corresponding channels, and provide the ATE with a plurality of test result signals received from each of the DUTs in response to the duplicated test signals. The synchronization signal generator receives a plurality of status signals from each of the DUTs and provides a timing synchronization signal to the ATE. Each of the status signals indicates a completion of a test operation in one of the DUTs, the test operation is associated with the test signal, and the synchronization signal generator activates the timing synchronization signal when all of the status signals indicate the completion of the test operation.