公开(公告)号：US20220157990A1

公开(公告)日：2022-05-19

申请号：US17587402

申请日：2022-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Ki Hwan KIM ,  Su Jin JUNG ,  Bong Soo KIM ,  Young Dae CHO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/24

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

公开(公告)号：US20200220015A1

公开(公告)日：2020-07-09

申请号：US16598012

申请日：2019-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Ki Hwan KIM ,  Su Jin JUNG ,  Bong Soo KIM ,  Young Dae CHO

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

公开(公告)号：US20210013046A1

公开(公告)日：2021-01-14

申请号：US17032356

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min PARK ,  Se Myeong JANG ,  Bong Soo KIM ,  Je Min PARK

IPC: H01L21/308 ,  H01L21/033

Abstract: A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.

公开(公告)号：US20200161294A1

公开(公告)日：2020-05-21

申请号：US16660976

申请日：2019-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Jin LEE ,  Ji Young KIM ,  Bong Soo KIM ,  Hyeon Kyun NOH ,  Moon Young JEONG

IPC: H01L27/06 ,  H01L29/22 ,  H01L27/12 ,  H01L27/108

Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate, an active region defined by an isolation film in the first substrate, an oxide semiconductor layer on the first substrate in the active region, and not comprising silicon, a recess inside the oxide semiconductor layer, and a gate structure filling the recess, comprising a gate electrode and a capping film on the gate electrode, and having an upper surface on a same plane as an upper surface of the active region.

公开(公告)号：US20200035499A1

公开(公告)日：2020-01-30

申请号：US16250180

申请日：2019-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min PARK ,  Se Myeong JANG ,  Bong Soo KIM ,  Je Min PARK

IPC: H01L21/308 ,  H01L21/033

Abstract: A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.

公开(公告)号：US20180158911A1

公开(公告)日：2018-06-07

申请号：US15887773

申请日：2018-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro SASAKI ,  Bong Soo KIM ,  Tae Gon KIM ,  Yoshiya MORIYAMA ,  Seung Hyun SONG ,  Alexander SCHMIDT ,  Abraham YOO ,  Heung Soon LEE ,  Kyung In CHOI

IPC: H01L29/10 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/2236 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

公开(公告)号：US20210202486A1

公开(公告)日：2021-07-01

申请号：US17201121

申请日：2021-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Hwan KIM ,  Ji Young KIM ,  Bong Soo KIM

IPC: H01L27/108 ,  H01L49/02

Abstract: A semiconductor device includes a plurality of lower electrode structures disposed on a substrate, and a supporter pattern disposed between pairs of lower electrode structures of the plurality of lower electrode structures. The semiconductor device further includes a capacitor dielectric layer disposed on surfaces of each of the plurality of lower electrode structures and the supporter pattern, and an upper electrode disposed on the capacitor dielectric layer. The plurality of lower electrode structures includes a first lower electrode and a second lower electrode disposed on the first lower electrode and having a cylindrical shape. The first lower electrode has a pillar shape. The first lower electrode includes an insulating core. The insulating core is disposed in the first lower electrode. An outer side surface of the first lower electrode and an outer side surface of the second lower electrode are coplanar.

公开(公告)号：US20170373151A1

公开(公告)日：2017-12-28

申请号：US15424081

申请日：2017-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro SASAKI ,  Bong Soo KIM ,  Tae Gon KIM ,  Yoshiya MORIYAMA ,  Seung Hyun SONG ,  Alexander SCHMIDT ,  Abraham YOO ,  Heung Soon LEE ,  Kyung In CHOI

IPC: H01L29/10 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/2236 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.