公开(公告)号：US20250138940A1

公开(公告)日：2025-05-01

申请号：US18639856

申请日：2024-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwasuk Cho ,  Seungwoo Yu ,  Byungkwan Chun

IPC: G06F11/10

Abstract: A nonvolatile memory device includes a plurality of latch groups, an address controller, an encoder, and a buffer. The address controller controls an input address and an output address to indicate one of the plurality of latch groups. The encoder receives sector data from a latch group corresponding to the output address among the plurality of latch groups and also compresses the received sector data. The buffer stores the compressed sector data. Among the plurality of latch groups, the compressed sector data stored in the buffer is overwritten in a latch group corresponding to the input address.

公开(公告)号：US12182419B2

公开(公告)日：2024-12-31

申请号：US18184319

申请日：2023-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woohyun Kang ,  Su Chang Jeon ,  Suhyun Kim ,  Hyuna Kim ,  Youngdeok Seo ,  Hyunkyo Oh ,  Donghoo Lim ,  Byungkwan Chun

IPC: G06F11/00 ,  G06F3/06

Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes providing a read command to the non-volatile memory device, receiving first read data and first distribution information corresponding to the read command from the non-volatile memory device, determining whether an error of the first read data is uncorrectable, and updating offset information of a history table in the storage controller based on the first distribution information, in response to determining that the error of the first read data is correctable.

公开(公告)号：US11736098B2

公开(公告)日：2023-08-22

申请号：US17866517

申请日：2022-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon ,  Byungkwan Chun ,  Byunghoon Jeong

IPC: H03K5/14 ,  H03L7/081 ,  H03K5/135 ,  H03K5/00

CPC classification number: H03K5/14 ,  H03K5/135 ,  H03L7/0816 ,  H03K2005/00247

Abstract: A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

公开(公告)号：US20250094062A1

公开(公告)日：2025-03-20

申请号：US18968373

申请日：2024-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woohyun Kang ,  Su Chang Jeon ,  Suhyun Kim ,  Hyuna Kim ,  Youngdeok Seo ,  Hyunkyo Oh ,  Donghoo Lim ,  Byungkwan Chun

IPC: G06F3/06

Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes providing a read command to the non-volatile memory device, receiving first read data and first distribution information corresponding to the read command from the non-volatile memory device, determining whether an error of the first read data is uncorrectable, and updating offset information of a history table in the storage controller based on the first distribution information, in response to determining that the error of the first read data is correctable.

公开(公告)号：US20240012569A1

公开(公告)日：2024-01-11

申请号：US18184319

申请日：2023-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woohyun Kang ,  Su Chang Jeon ,  Suhyun Kim ,  Hyuna Kim ,  Youngdeok Seo ,  Hyunkyo Oh ,  Donghoo Lim ,  Byungkwan Chun

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes providing a read command to the non-volatile memory device, receiving first read data and first distribution information corresponding to the read command from the non-volatile memory device, determining whether an error of the first read data is uncorrectable, and updating offset information of a history table in the storage controller based on the first distribution information, in response to determining that the error of the first read data is correctable.

公开(公告)号：US20230179193A1

公开(公告)日：2023-06-08

申请号：US17866517

申请日：2022-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon ,  Byungkwan Chun ,  Byunghoon Jeong

IPC: H03K5/14 ,  H03K5/135 ,  H03L7/081

CPC classification number: H03K5/14 ,  H03K5/135 ,  H03L7/0816 ,  H03K2005/00247

Abstract: A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

公开(公告)号：US11600336B2

公开(公告)日：2023-03-07

申请号：US17332350

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Byungkwan Chun

IPC: G11C16/24 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A nonvolatile memory device includes a memory cell array including memory cells and a page buffer circuit. The page buffer circuit includes page buffer units and cache latches. The cache latches are spaced apart from the page buffer units in a first horizontal direction, and correspond to respective ones of the plurality of page buffer units. Each of the page buffer units includes a pass transistor connected to each sensing node and driven in response to a pass control signal. The page buffer circuit being configured to perform a data transfer operation, based on performing a first data output operation to output data, provided from a first portion of page buffer units, from a first portion of cache latches to a data input/output (I/O) line, the data transfer operation configured to dump sensed data from a second portion of page buffer units to a second portion of cache latches.