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    Nonvolatile memory and storage device including same
    1.
    发明授权
    Nonvolatile memory and storage device including same 有权

    公开(公告)号：US12002514B2

    公开(公告)日：2024-06-04

    申请号：US17706097

    申请日：2022-03-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Won Park ,  Won-Taeck Jung ,  Han-Jun Lee ,  Su Chang Jeon

    IPC: G11C8/12 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3459 ,  G11C8/12

    Abstract: A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.

    Memory device and method of reading data
    2.
    发明授权
    Memory device and method of reading data 有权

    公开(公告)号：US11955183B2

    公开(公告)日：2024-04-09

    申请号：US17827852

    申请日：2022-05-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Su Chang Jeon ,  Seung Bum Kim ,  Ji Young Lee

    IPC: G11C16/24 ,  G11C16/12 ,  G11C16/26

    CPC classification number: G11C16/24 ,  G11C16/12 ,  G11C16/26

    Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

    Memory device and method of reading data
    4.
    发明授权
    Memory device and method of reading data 有权

    公开(公告)号：US11107537B2

    公开(公告)日：2021-08-31

    申请号：US16987658

    申请日：2020-08-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Su Chang Jeon ,  Seung Bum Kim ,  Ji Young Lee

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C16/10 ,  H01L27/115 ,  G11C16/08

    Abstract: A non-volatile memory includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array region in the memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines in the memory cell region, an outer memory cell string in the memory cell region including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O) circuit in the peripheral circuit region including a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

    Nonvolatile memory device and operation method thereof
    6.
    发明授权
    Nonvolatile memory device and operation method thereof 有权

    公开(公告)号：US12165694B2

    公开(公告)日：2024-12-10

    申请号：US18223783

    申请日：2023-07-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Su Chang Jeon ,  Woohyun Kang ,  Seungkyung Ro ,  Sangkwon Moon ,  Heewon Lee

    IPC: G06F3/06 ,  G11C11/408

    Abstract: Disclosed is a nonvolatile memory device which include a memory cell array including a plurality of memory cells connected to a plurality of word lines, an address decoder that controls a selected word line among the plurality of word lines based on an address received from an external device including a first temperature sensor, a second temperature sensor that measures a read temperature of first memory cells connected to the selected word line from among the plurality of memory cells, and a temperature compensation circuit that calculates a read level offset based on the read temperature and a program temperature of the first memory cells measured by the first temperature sensor and generates a compensation read voltage based on the read level offset. The address decoder is further configured to provide the compensation read voltage to the selected word line.

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