公开(公告)号：US10903324B2

公开(公告)日：2021-01-26

申请号：US16205851

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US11705503B2

公开(公告)日：2023-07-18

申请号：US17038004

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum Kim ,  MunHyeon Kim ,  Hyoung Sub Kim ,  Tae Jin Park ,  Kwan Heum Lee ,  Chang Woo Noh ,  Maria Toledano Lu Que ,  Hong Bae Park ,  Si Hyung Lee ,  Sung Man Whang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US11710741B2

公开(公告)日：2023-07-25

申请号：US17243943

申请日：2021-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang ,  Sang Hoon Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L27/0924 ,  H01L21/0337 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/785 ,  H01L2029/7858

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

公开(公告)号：US20200091152A1

公开(公告)日：2020-03-19

申请号：US16405174

申请日：2019-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang ,  Sang Hoon Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

公开(公告)号：US20250089352A1

公开(公告)日：2025-03-13

申请号：US18434041

申请日：2024-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Byeong Hee Son

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor includes a substrate, first and second active patterns that are on the substrate and extend in a first horizontal direction, a first gate electrode that is on the first active pattern and extends in a second horizontal direction, a second gate electrode that is on the second active pattern and extends in the second horizontal direction, an active cut trench that extends in the second horizontal direction and is between the first gate electrode and the second gate electrode, an active cut including a first layer and a second layer on the first layer, a first source/drain region that is between the first gate electrode and the active cut and is on the first active pattern, and a first source/drain contact that is on the first source/drain region, where at least a part of the first source/drain contact overlaps the first layer in a vertical direction.

公开(公告)号：US20240421189A1

公开(公告)日：2024-12-19

申请号：US18596179

申请日：2024-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Jin Park ,  Myung Gil Kang ,  Dong Won Kim ,  Chang Woo Noh ,  Yu Jin Jeon

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor devices. An example semiconductor device includes a substrate including first and second regions, a first bridge pattern extending in a first direction on the first region, a first gate structure extending in a second direction intersecting the first direction, first epitaxial patterns connected to the first bridge pattern on side surfaces of the first gate structure, first inner spacers interposed between the substrate and the first bridge pattern and between the first gate structure and the first epitaxial patterns, a second bridge pattern extending in the first direction on the second region, a second gate structure extending in the second direction, second epitaxial patterns connected to the second bridge pattern on side surfaces of the second gate structure, and second inner spacers interposed between the substrate and the second bridge pattern and between the second gate structure and the second epitaxial patterns.

公开(公告)号：US11699728B2

公开(公告)日：2023-07-11

申请号：US17127230

申请日：2020-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Woo Noh ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7853 ,  H01L2029/7858

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US11133383B2

公开(公告)日：2021-09-28

申请号：US16741868

申请日：2020-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Woo Noh ,  Dong Il Bae ,  Geum Jong Bae

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/84 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device including a buried insulating layer on a substrate; a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer including a first material; a channel pattern on the lower semiconductor layer, the channel pattern being spaced apart from the lower semiconductor layer and including a second material different from the first material; and a gate electrode surrounding at least a portion of the channel pattern.

公开(公告)号：US11024628B2

公开(公告)日：2021-06-01

申请号：US16405174

申请日：2019-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang ,  Sang Hoon Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.