公开(公告)号：US09941014B2

公开(公告)日：2018-04-10

申请号：US14477347

申请日：2014-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： ChulHo Lee

IPC: G06F12/02 ,  G11C16/32 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/32 ,  G11C11/5628 ,  G11C16/10 ,  G11C2207/2245

Abstract: A nonvolatile memory device includes a memory cell array having a normal area and a temporary area. A page buffer stores data to be written to the normal area in a normal program operation and store a temporary data to be written to the temporary area in a temporary program operation. A control logic performs the normal program operation including a plurality of program loops. The control logic receives a suspend command before the normal program operation is completed and determines, in response to the suspend command, whether to complete the normal program operation or to suspend the normal operation and perform the temporary program operation based on a reference value representing a time for performing at least one program loop of the plurality of program loops.

公开(公告)号：US08988928B2

公开(公告)日：2015-03-24

申请号：US13947466

申请日：2013-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： ChulHo Lee

IPC: G11C7/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0064 ,  G11C2213/72

Abstract: An operating method of a multi-bit-per-cell nonvolatile memory device, e.g., first and second variable resistance memory cells connected to one of word lines. The operating method may include receiving first to fourth data sequentially, providing a first program current to the first variable resistance memory cell to program the first and second data to the first variable resistance memory cell, and providing a second program current to the second variable resistance memory cell to program the third and fourth data to the second variable resistance memory cell after verifying whether an actual resistance of the programmed first variable resistance memory cell is within an intended resistance distribution.

Abstract translation: 多比特单元非易失性存储器件的操作方法，例如连接到字线之一的第一和第二可变电阻存储器单元。 操作方法可以包括顺序地接收第一到第四数据，向第一可变电阻存储单元提供第一编程电流，以将第一和第二数据编程到第一可变电阻存储单元，并向第二可变电阻提供第二编程电流 存储单元，用于在验证所编程的第一可变电阻存储单元的实际电阻是否在预期电阻分布内之前将第三和第四数据编程到第二可变电阻存储单元。

公开(公告)号：US09025384B2

公开(公告)日：2015-05-05

申请号：US13738983

申请日：2013-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： ChulHo Lee ,  Eun-Jin Yun ,  BoGeun Kim

IPC: G11C16/04 ,  G11C16/10 ,  G11C13/00 ,  G11C16/26 ,  G06F13/16 ,  G11C11/16

CPC classification number: G11C16/10 ,  G06F13/1694 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/26

Abstract: A memory system including a first memory of a first type; a second memory of a second type; and a controller configured to control the first memory and the second memory. The first type and second type are different, and the controller is configured to control the first memory and the second memory according to substantially the same command sequence.

Abstract translation: 一种存储器系统，包括第一类型的第一存储器; 第二种类型的第二存储器; 以及控制器，被配置为控制所述第一存储器和所述第二存储器。 第一类型和第二类型不同，并且控制器被配置为根据基本上相同的命令序列来控制第一存储器和第二存储器。