公开(公告)号：US09001887B2

公开(公告)日：2015-04-07

申请号：US13958835

申请日：2013-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hyun Kim ,  Hyun-Sang Park ,  Si-hwa Lee ,  Do-hyung Kim

IPC: H04N7/12 ,  H04N19/23 ,  H04N19/43 ,  H04N19/433

CPC classification number: H04N19/23 ,  H04N19/43 ,  H04N19/433

Abstract: Provided are a method and apparatus for buffering image data for motion compensation. One of two buffers of a double register array buffer, i.e., a first buffer, is selected as a buffer in which data corresponding to a row of a block of an image is to be written and the other of the double register array buffer is selected as a buffer from which data corresponding to another row of the block is to be read, thereby speeding up motion compensation processing when compared with the use of a single register array buffer.

Abstract translation: 提供一种用于缓冲用于运动补偿的图像数据的方法和装置。 选择双寄存器阵列缓冲器（即，第一缓冲器）的两个缓冲器之一作为缓冲器，其中与图像块的行相对应的数据将被写入，并且选择双寄存器阵列缓冲器中的另一个 作为与块的另一行对应的数据的缓冲器，与使用单个寄存器阵列缓冲器相比，加速运动补偿处理。

公开(公告)号：US09799404B2

公开(公告)日：2017-10-24

申请号：US15357291

申请日：2016-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Doo-Hyun Kim ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/06 ,  G11C16/34 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/12

CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0688 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3459 ,  H01L27/11582

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

公开(公告)号：US09514827B1

公开(公告)日：2016-12-06

申请号：US15018925

申请日：2016-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Doo-Hyun Kim ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  G11C16/26 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12

CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0688 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3459 ,  H01L27/11582

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

Abstract translation: 如下提供存储器件。 存储单元区域包括多个块，每个块包括多个NAND串。 控制逻辑基于相对于存储器单元区域的第一边缘的第一距离的较小距离和相对于存储器单元区域的第二边缘的第二距离，将多个块划分为多个块区域，以及 使用用于该操作的多个偏置操作参数组来控制在存储单元区域上执行的操作。 每个偏差集合与块区域之一相关联。

公开(公告)号：US09761315B2

公开(公告)日：2017-09-12

申请号：US15357291

申请日：2016-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Doo-Hyun Kim ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/06 ,  G11C16/34 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/12

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

公开(公告)号：US09812168B2

公开(公告)日：2017-11-07

申请号：US15044321

申请日：2016-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hyun Kim ,  Jae-Hyun Kim ,  Byeong-Jun Kim ,  Sang-Soo Park ,  Jun-Soo Lee ,  Ho-Chul Hwang

IPC: H04N9/80 ,  H04N5/93 ,  G11B27/031

CPC classification number: G11B27/031

Abstract: The present disclosure provides an electronic device and method for playing image data. The method for playing back image data in an electronic device includes storing an audiovisual (A/V) data for a predetermined period of time in a memory of the electronic device. The electronic device plays back the A/V data, wherein upon playing back, by the electronic device, the A/V data comprises analyzing an audio signal of the A/V data dynamically to select one of a plurality of sound effects based on the analyzed audio signal. The A/V data is played back by applying the selected sound effect to at least a part of the A/V signal.