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    Semiconductor package
    1.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12142544B2

    公开(公告)日：2024-11-12

    申请号：US17734700

    申请日：2022-05-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehwan Kim ,  Young-Deuk Kim ,  Jae Choon Kim ,  Kyung Suk Oh ,  Eungchang Lee

    IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L23/498

    Abstract: A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

    SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250118620A1

    公开(公告)日：2025-04-10

    申请号：US18732444

    申请日：2024-06-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-Deuk Kim ,  Heejung Hwang

    IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

    Abstract: Disclosed is a semiconductor package including a wiring substrate, an external connection terminal on a bottom surface of the wiring substrate, an interposer substrate on a top surface of the wiring substrate, a first semiconductor chip on the interposer substrate, and a first chip stack on the interposer substrate and horizontally spaced apart from the first semiconductor chip. The wiring substrate includes a core, an upper redistribution layer covering a top surface of the core, and a lower redistribution layer covering a bottom surface of the core. The core includes core through vias vertically penetrating the core, and a first thermal radiation structure below the first chip stack and in the core. The first thermal radiation structure is electrically insulated from the upper and lower redistribution layers. A thermal conductivity of the first thermal radiation structure is greater than that of the core.

    Semiconductor package and display apparatus using the same
    5.
    发明授权
    Semiconductor package and display apparatus using the same 有权
    半导体封装及使用其的显示装置

    公开(公告)号：US08872337B2

    公开(公告)日：2014-10-28

    申请号：US14106912

    申请日：2013-12-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Deuk Kim ,  Ji-Chul Kim

    IPC: H01L27/00 ,  H01L23/36

    CPC classification number: H01L23/36 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/49894 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12044 ,  H01L2924/00

    Abstract: A semiconductor package includes a flexible base film having a first surface opposing a second surface, a semiconductor chip mounted on the first surface of the base film, and a touch sensing structure including at least one conductive pattern adjacent to the semiconductor chip. The at least one conductive pattern is disposed through the base film and has a surface exposed at the second surface of the base film. A contact condition of the semiconductor package is determined based on detection of a conductive path between the at least one conductive pattern and a conductive frame or support surface of the semiconductor package. The contact condition provides an indication of heat dissipation that may be expected to occur for the chip during operation.

    Abstract translation: 半导体封装包括具有与第二表面相对的第一表面的柔性基膜，安装在基膜的第一表面上的半导体芯片，以及包括与半导体芯片相邻的至少一个导电图案的触摸感测结构。 所述至少一个导电图案设置穿过所述基底膜并具有在所述基底膜的第二表面处露出的表面。 基于对至少一个导电图案和半导体封装的导电框架或支撑表面之间的导电路径的检测来确定半导体封装的接触状态。 接触条件提供可能预期在操作期间芯片发生的散热的指示。

    Electronic device and method of manufacturing the electronic device
    6.
    发明授权
    Electronic device and method of manufacturing the electronic device 有权

    公开(公告)号：US10707196B2

    公开(公告)日：2020-07-07

    申请号：US16162598

    申请日：2018-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Choon Kim ,  Young-Deuk Kim ,  Woo-Hyun Park

    IPC: H01L23/02 ,  H01L25/18 ,  H05K1/18 ,  H01L23/427 ,  H01L23/48 ,  H01L25/065 ,  H01L23/538 ,  H01L23/367

    Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the second electronic product in the plan view, wherein the overlapping area of the solid thermal conductive member with the second electronic product is greater than 50% of an area of the second electronic product in the plan view.

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