公开(公告)号：US20240321847A1

公开(公告)日：2024-09-26

申请号：US18605956

申请日：2024-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunsu Lee

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L25/16 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H10B80/00 ,  H01L23/481 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/182 ,  H01L2924/19106

Abstract: A semiconductor package includes a first substrate; a first chip structure disposed above the first substrate in a vertical direction; a second chip structure disposed above the first substrate and spaced apart from the first chip structure in a first horizontal direction perpendicular to the vertical direction; an underfill material layer disposed between the second chip structure and the first substrate; and a first protrusion extending from the first substrate in the vertical direction and extending in a second horizontal direction perpendicular to the vertical direction and the first horizontal direction along at least one side surface of the underfill material layer, where a side surface of the first protrusion contacts the underfill material layer.

公开(公告)号：US20240339336A1

公开(公告)日：2024-10-10

申请号：US18538631

申请日：2023-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu Lee

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/83007 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2225/06568

Abstract: A semiconductor package includes: a substrate including a first surface and a second surface opposite the first surface, a bottom die electrically connected to first bonding pads on the first surface of the substrate; a top die on the bottom die and electrically connected to second bonding pads on the first surface of the substrate by wires, an underfill in a gap between the substrate and the bottom die, an underfill dam surrounding the first bonding pads and the second bonding pads on the first surface of the substrate and is configured to restrict diffusion of the underfill, a mold that at least partially covers elements on the first surface of the substrate, and a plurality of solder balls on the second surface of the substrate. The second bond pads and a part of each of the wires bonded to the second bonding pads are immersed in the underfill.

公开(公告)号：US20240136272A1

公开(公告)日：2024-04-25

申请号：US18340193

申请日：2023-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49833 ,  H01L25/105 ,  H10B80/00 ,  H01L24/16 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package including: a front redistribution structure including an insulating layer defining an upper surface, a lower surface opposing the upper surface, and a side surface, front redistribution layers including a first redistribution layer on a first level adjacent to the lower surface and second redistribution layers on a second level higher than the first level relative to the lower surface, the second redistribution layers having an inner redistribution layer and an outer redistribution layer, a recess exposing at least a portion of the outer redistribution layer, and a dam on at least one side of the recess; connection bumps including a first bump electrically connected to the first redistribution layer and a second bump electrically connected to the outer redistribution layer within the recess; and an underfill that extends along a side surface of the second bump and a side surface of the dam within the recess.

公开(公告)号：US12272661B2

公开(公告)日：2025-04-08

申请号：US17564689

申请日：2021-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu Lee ,  Dongho Kim ,  Jiyong Park ,  Jeonghyun Lee

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first bonding pad on a first surface of a first substrate, a first through electrode penetrating through the first substrate and electrically connected to the first bonding pad, a first recess with a desired depth in the first substrate from a second surface of the first substrate and exposing an end portion of the first through electrode, and a second bonding pad in the first recess and electrically connected to the first through electrode, a second semiconductor chip stacked on the second surface of the first substrate and including a third bonding pad on a third surface of a second substrate, and a conductive connection member between the second bonding pad and the third bonding pad. At least a portion of the conductive connection member may be in the first recess.

公开(公告)号：US20240096840A1

公开(公告)日：2024-03-21

申请号：US18370283

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu Lee ,  Jongbo Shim ,  Sungeun Pyo

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0801 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1434 ,  H10B80/00

Abstract: A semiconductor device includes a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view; a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer; a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode; a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate; and a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode. The first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view.

公开(公告)号：US20230139141A1

公开(公告)日：2023-05-04

申请号：US18050705

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doyoung Jang ,  Eunsu Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor package includes a first package substrate, a semiconductor chip on the first package substrate, a second package substrate over the first package substrate and the semiconductor chip, and a plurality of core structures and a plurality of solder balls. The core structures and the solder balls are between the first package substrate and the second package substrate, a first portion of the plurality of core structures and the plurality of solder balls are apart from the semiconductor chip in a first dimension direction, and a second portion of the plurality of core structures and the plurality of solder balls are apart from the semiconductor chip in a second dimension direction that is different than the first dimension direction. The semiconductor package includes a plurality of strip guides between the semiconductor chip and the plurality of core structures, and in parallel with a periphery of the semiconductor chip.

公开(公告)号：US20250038080A1

公开(公告)日：2025-01-30

申请号：US18675558

申请日：2024-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

Abstract: Provided is a semiconductor package including a first substrate, a first semiconductor package on the first substrate and including a first semiconductor chip, and a second semiconductor package on the first substrate spaced apart from the first semiconductor package in a horizontal direction, and including one or more semiconductor chips and a molding layer on the one or more semiconductor chips, wherein the molding layer includes a molding member and one or more dummy posts extending into the molding member in a vertical direction and configured to be electrically insulated.

公开(公告)号：US20240234286A9

公开(公告)日：2024-07-11

申请号：US18340193

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49833 ,  H01L25/105 ,  H10B80/00 ,  H01L24/16 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package including: a front redistribution structure including an insulating layer defining an upper surface, a lower surface opposing the upper surface, and a side surface, front redistribution layers including a first redistribution layer on a first level adjacent to the lower surface and second redistribution layers on a second level higher than the first level relative to the lower surface, the second redistribution layers having an inner redistribution layer and an outer redistribution layer, a recess exposing at least a portion of the outer redistribution layer, and a dam on at least one side of the recess; connection bumps including a first bump electrically connected to the first redistribution layer and a second bump electrically connected to the outer redistribution layer within the recess; and an underfill that extends along a side surface of the second bump and a side surface of the dam within the recess.

公开(公告)号：US20240203942A1

公开(公告)日：2024-06-20

申请号：US18354928

申请日：2023-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doyoung Jang ,  Eunsu Lee ,  Daeyoung Jung

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/10

CPC classification number: H01L25/0655 ,  H01L23/481 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/48229 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip on the first substrate, and second semiconductor chips on the first substrate and adjacent sides of the first semiconductor chip, each of the second semiconductor chips has an elongated shape extending along one of the sides of the first semiconductor chip which is adjacent thereto, and a width of each of the second semiconductor chips is smaller than a width of the first semiconductor chip.