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    Fuse data reading circuit having multiple reading modes and related devices, systems and methods
    2.
    发明授权
    Fuse data reading circuit having multiple reading modes and related devices, systems and methods 有权
    具有多种读取模式和相关设备，系统和方法的保险丝数据读取电路

    公开(公告)号：US09343175B2

    公开(公告)日：2016-05-17

    申请号：US13835319

    申请日：2013-03-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gil-Su Kim ,  Jong-Min Oh ,  Sung-Min Seo ,  Je-Min Ryu ,  Seong-Jin Jang

    IPC: G11C17/00 ,  G11C17/18 ,  G11C7/14 ,  G11C17/16 ,  G11C29/00

    CPC classification number: G11C17/18 ,  G11C7/14 ,  G11C17/16 ,  G11C29/789

    Abstract: A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.

    Abstract translation: 熔丝数据读取电路被配置为以多读取模式读取熔丝数据。 熔丝数据可以存储在包括被配置为存储熔丝数据的多个熔丝单元的熔丝阵列中。 熔丝数据读取电路可以包括感测单元，其被配置为感测存储在熔丝阵列的熔丝单元中的熔丝数据，以及控制器，被配置为控制读取存储在熔丝单元中的熔丝数据的操作。 控制器根据熔丝数据读取操作期间的操作周期设置感测熔丝数据的不同感测条件以读取熔丝数据。 方法包括操作和使用熔丝数据读取电路。

    MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE MEMORY DEVICE 有权
    存储器件，其操作方法和具有存储器件的电子器件

    公开(公告)号：US20130322149A1

    公开(公告)日：2013-12-05

    申请号：US13771633

    申请日：2013-02-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Je-Min Ryu ,  Gil-Su Kim ,  Jong-Min Oh ,  Sung-Min Seo ,  Ho-Young Song ,  Yong-Ho Cho

    IPC: G11C17/16 ,  G11C17/18

    CPC classification number: G11C17/16 ,  G11C7/1045 ,  G11C17/18 ,  G11C29/802

    Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

    Abstract translation: 存储器件包括存储单元阵列和熔丝器件。 保险丝装置包括熔丝单元阵列和熔丝控制电路。 熔丝单元阵列包括存储与熔丝控制电路的操作相关联的第一数据的第一熔丝单元子阵列和存储与存储器件的操作相关联的第二数据的第二熔丝单元子阵列。 熔丝控制电路电耦合到第一和第二熔丝单元子阵列，并且被配置为分别从第一和第二熔丝单元子阵列读取第一和第二数据。

    Semiconductor memory device having OTP cell array
    5.
    发明授权
    Semiconductor memory device having OTP cell array 有权
    具有OTP单元阵列的半导体存储器件

    公开(公告)号：US09293218B2

    公开(公告)日：2016-03-22

    申请号：US14049399

    申请日：2013-10-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Je-Min Yu ,  Sung-Min Seo ,  Ho-Young Song ,  Gil-Su Kim ,  Jong-Min Oh

    IPC: G11C16/04 ,  G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

    CPC classification number: G11C17/08 ,  G11C16/04 ,  G11C16/0483 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785

    Abstract: Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

    Abstract translation: 提供了一种半导体存储器件。 该半导体包括一个可编程（OTP）单元阵列，一个会聚电路和一个读出放大器电路。 OTP单元阵列包括连接到多个位线的多个OTP单元，每个位线沿第一方向延伸。 收敛包括接触第一位线和第二位线的公共节点。 感测放大器电路包括连接到公共节点的读出放大器，该读出放大器配置成放大公共节点的信号。

    Memory device, method of operating the same, and electronic device having the memory device
    6.
    发明授权
    Memory device, method of operating the same, and electronic device having the memory device 有权
    存储装置，其操作方法和具有存储装置的电子装置

    公开(公告)号：US08897055B2

    公开(公告)日：2014-11-25

    申请号：US13771633

    申请日：2013-02-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Je-Min Ryu ,  Gil-Su Kim ,  Jong-Min Oh ,  Sung-Min Seo ,  Ho-Young Song ,  Yong-Ho Cho

    IPC: G11C17/16 ,  G11C29/00 ,  G11C7/10 ,  G11C17/18

    CPC classification number: G11C17/16 ,  G11C7/1045 ,  G11C17/18 ,  G11C29/802

    Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

    Abstract translation: 存储器件包括存储单元阵列和熔丝器件。 保险丝装置包括熔丝单元阵列和熔丝控制电路。 熔丝单元阵列包括存储与熔丝控制电路的操作相关联的第一数据的第一熔丝单元子阵列和存储与存储器件的操作相关联的第二数据的第二熔丝单元子阵列。 熔丝控制电路电耦合到第一和第二熔丝单元子阵列，并且被配置为分别从第一和第二熔丝单元子阵列读取第一和第二数据。

    Semiconductor memory device including sensing verification unit
    7.
    发明授权
    Semiconductor memory device including sensing verification unit 有权
    半导体存储器件包括检测验证单元

    公开(公告)号：US09165673B2

    公开(公告)日：2015-10-20

    申请号：US13795567

    申请日：2013-03-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Je-Min Yu ,  Ho-Young Song ,  Sung-Min Seo ,  Sang-Joon Hwang

    IPC: G11C17/00 ,  G11C17/16 ,  G11C17/18

    CPC classification number: G11C17/00 ,  G11C17/16 ,  G11C17/18

    Abstract: A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.

    Abstract translation: 半导体存储器件包括：存储单元阵列，被配置为存储包括验证码的数据; 感测单元，被配置为感测存储的包括验证码的数据; 以及验证单元，被配置为基于感测条件来确定所述感测单元是否能够感测所存储的数据，其中所述验证单元被配置为基于所述感测条件来确定所述感测单元是否能够感测所存储的数据，以及 由感测单元感测的验证码的值。

    Devices and methods for deciding data read start
    8.
    发明授权
    Devices and methods for deciding data read start 有权
    用于决定数据读取开始的设备和方法

    公开(公告)号：US09123407B2

    公开(公告)日：2015-09-01

    申请号：US14073987

    申请日：2013-11-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Je-Min Ryu ,  Sung-Min Seo ,  Ju-Seop Park

    IPC: G11C7/22 ,  G11C7/10 ,  G11C29/02 ,  G11C7/20 ,  G11C7/08 ,  G11C29/44

    CPC classification number: G11C7/20 ,  G11C7/1063 ,  G11C7/22 ,  G11C7/222 ,  G11C29/028 ,  G11C2029/4402

    Abstract: A data read start decision device includes: a storing circuit configured to store code key data; a read check circuit configured to output a read start signal in response to code key data read from the storing circuit, and a controller configured to start reading environment setting data from the storing circuit in response to the read start signal. The read check circuit is configured to at least one of: receive the read start signal from the controller and transfer the read start signal to the controller in response to the read code key data; and generate the read start signal based on the read code key data and output the read start signal to the controller.

    Abstract translation: 数据读取开始判定装置包括：存储电路，被配置为存储代码密钥数据; 读取检查电路，被配置为响应于从存储电路读取的代码密钥数据输出读取开始信号，以及控制器，被配置为响应于读取的开始信号从存储电路开始读取环境设置数据。 读取检查电路被配置为以下中的至少一个：从控制器接收读取开始信号并响应于读取代码密钥数据将读取的开始信号传送到控制器; 并根据读取的代码键数据生成读取开始信号，并将读出的开始信号输出到控制器。

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