公开(公告)号：US20140057430A1

公开(公告)日：2014-02-27

申请号：US14072777

申请日：2013-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

IPC: H01L21/768

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract translation: 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。

公开(公告)号：US20130330881A1

公开(公告)日：2013-12-12

申请号：US13772427

申请日：2013-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Woo PARK ,  Seok-Hyun LEE ,  Ho-Geon SONG

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/568 ,  H01L24/19 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Provided are a double-sided adhesive tape, semiconductor packages, and methods of fabricating the packages. A method of fabricating semiconductor packages includes providing a double-sided adhesive tape on a top surface of a carrier, the double-sided adhesive tape including a first adhesive layer and a second adhesive layer stacked on the first adhesive layer, the first adhesive layer of the double-sided adhesive tape being in contact with the top surface of the carrier, adhering active surfaces of a plurality of semiconductor chips onto the second adhesive layer of the double-sided adhesive tape, separating the first adhesive layer from the second adhesive layer such that the second adhesive layer remains on the active surfaces of the semiconductor chips, patterning the second adhesive layer to form first openings that selectively expose the active surfaces of the semiconductor chips, and forming first conductive components on the second adhesive layer to fill the first openings.

Abstract translation: 提供双面胶带，半导体封装以及制造封装的方法。 制造半导体封装的方法包括在载体的顶表面上提供双面胶带，所述双面胶带包括第一粘合剂层和层叠在第一粘合剂层上的第二粘合剂层，第一粘合剂层 所述双面胶带与所述载体的顶表面接触，将多个半导体芯片的活性表面粘合到所述双面胶带的第二粘合剂层上，从而将所述第一粘合剂层与所​​述第二粘合层分离， 第二粘合剂层保留在半导体芯片的有效表面上，图案化第二粘合剂层以形成选择性地暴露半导体芯片的有效表面的第一开口，以及在第二粘合剂层上形成第一导电部件以填充第一开口 。

公开(公告)号：US20140196280A1

公开(公告)日：2014-07-17

申请号：US14217744

申请日：2014-03-18

Applicant: Samsung Electronics Co., Ltd

Inventor： Chang-Seong JEON ,  Ho-Geon SONG ,  Mitsuo UMEMOTO ,  Sang-Sick PARK

IPC: H01L23/00 ,  H01L21/67

CPC classification number: H01L24/74 ,  H01L21/67 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32151 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/7501 ,  H01L2224/7515 ,  H01L2224/7525 ,  H01L2224/75252 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/759 ,  H01L2224/7598 ,  H01L2224/7901 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/53178 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed.

Abstract translation: 制造倒装芯片封装的方法和装置包括将焊剂点到封装衬底的第一预备凸块上，通过焊剂将第一半导体芯片的初步凸点附着到封装衬底的第一初步凸块上，点焊焊剂 封装衬底的第二初步凸块，以及通过焊剂将第二半导体芯片的预备凸块附接到封装衬底的第二初级凸块。 因此，可以抑制在封装衬底的初步凸块上的焊剂的蒸发。