公开(公告)号：US09859022B2

公开(公告)日：2018-01-02

申请号：US14722823

申请日：2015-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-joong Kim ,  Soo-hyeong Kim ,  Sang-hoon Shin ,  Ju-yun Jung ,  Ho-young Song ,  Kyo-min Sohn ,  Hae-suk Lee ,  Bu-il Jung ,  Han-vit Jeong

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.

公开(公告)号：US10014037B2

公开(公告)日：2018-07-03

申请号：US15490614

申请日：2017-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyo-min Sohn

IPC: G11C7/00 ,  G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22 ,  G11C7/12

CPC classification number: G11C7/1009 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2211/5647

Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

公开(公告)号：US10468092B2

公开(公告)日：2019-11-05

申请号：US16288626

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-ho Hyun ,  Kyo-min Sohn ,  Je-min Ryu ,  Ho-Seok Seol

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4093

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

公开(公告)号：US20190198087A1

公开(公告)日：2019-06-27

申请号：US16288626

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-ho HYUN ,  Kyo-min Sohn ,  Je-min Ryu ,  Ho-Seok Seol

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4087 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4093 ,  G11C2211/4061

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

公开(公告)号：US09640233B2

公开(公告)日：2017-05-02

申请号：US15206106

申请日：2016-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyo-min Sohn

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/16 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/1009 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2211/5647

Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

公开(公告)号：US09390780B2

公开(公告)日：2016-07-12

申请号：US14800256

申请日：2015-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyo-min Sohn

IPC: G11C7/00 ,  G11C11/16 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097

CPC classification number: G11C7/1009 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2211/5647

Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.