公开(公告)号：US20180151502A1

公开(公告)日：2018-05-31

申请号：US15583690

申请日：2017-05-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10

CPC分类号： H01L23/5389 ,  H01L23/3128 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13024 ,  H01L2224/17181 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/73101 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094

摘要： A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.

公开(公告)号：US09293430B2

公开(公告)日：2016-03-22

申请号：US14717606

申请日：2015-05-20

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Fucheng Chen

IPC分类号： H01L23/52 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02175 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0381 ,  H01L2224/03831 ,  H01L2224/04 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/06505 ,  H01L2224/08058 ,  H01L2224/08111 ,  H01L2224/08145 ,  H01L2224/10145 ,  H01L2224/1148 ,  H01L2224/1181 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/27831 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73101 ,  H01L2224/73104 ,  H01L2224/73201 ,  H01L2224/73204 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/81948 ,  H01L2224/83011 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2224/05 ,  H01L2224/13 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2224/80 ,  H01L2924/00

摘要： A chip includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a first dielectric region and a second dielectric region surrounding an outer periphery of the first dielectric region. A top surface of the first dielectric region is disposed below a top surface of the second dielectric region. The chip further includes a metal pad disposed in a through-hole in the first dielectric region and contacting a portion of the substrate.

摘要翻译： 芯片包括衬底和设置在衬底上的电介质层。 电介质层包括第一电介质区域和围绕第一电介质区域的外围的第二电介质区域。 第一电介质区域的顶表面设置在第二电介质区域的顶表面下方。 芯片还包括设置在第一电介质区域中的通孔中并与衬底的一部分接触的金属焊盘。

公开(公告)号：US20240243090A1

公开(公告)日：2024-07-18

申请号：US18618133

申请日：2024-03-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaekul LEE ,  Hyungsun JANG ,  Gayoung KIM ,  Minjeong SHIN

IPC分类号： H01L23/00 ,  H01L25/10

CPC分类号： H01L24/20 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/73101 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A semiconductor package includes a lower redistribution layer disposed on a lower surface of the semiconductor chip including an insulating layer, a redistribution pattern, a via, an under bump metal (UBM), and a post disposed on the redistribution pattern. The post vertically overlaps with the UBM. A mold layer is on the lower redistribution layer and surrounds the semiconductor chip. A connecting terminal is connected to the UBM. The UBM includes a first section contacting the redistribution pattern, and a second section contacting the insulating layer. The post has a ring shape having an inner surface and an outer surface when viewed in a top view. A maximum width of the inner surface is less than a maximum width of an upper surface of the first section. A maximum width of the outer surface is greater than the maximum width of the upper surface of the first section.

公开(公告)号：US11967563B2

公开(公告)日：2024-04-23

申请号：US17402734

申请日：2021-08-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31

CPC分类号： H01L23/5389 ,  H01L23/5286 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/105 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/562 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/17181 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73101 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012

摘要： A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

公开(公告)号：US20240030173A1

公开(公告)日：2024-01-25

申请号：US17867853

申请日：2022-07-19

申请人： NXP B.V.

发明人： Che Ming Fang ,  Kuan-Hsiang Mao ,  Yufu Liu ,  Wen Hung Huang

IPC分类号： H01L23/00

CPC分类号： H01L24/20 ,  H01L24/13 ,  H01L24/11 ,  H01L24/19 ,  H01L24/73 ,  H01L2224/13027 ,  H01L2224/11849 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/73101

摘要： An IC package includes one or more microelectronic devices, a plurality of package bumps disposed at a first side, and a metal structure electrically connecting at least a first device contact pad of a first microelectronic device and at least a first package bump of the plurality of package bumps. The metal structure includes an RDL trace extending between a first region aligned with the first device contact pad and a second region aligned with the first package bump, wherein the first package bump is mechanically and electrically connected directly to the second region of the RDL trace. The metal structure further includes a first via extending between the first region of the RDL trace and the first device contact pad and further includes a set of one or more support studs extending from the second region to a support surface facing the first side.

公开(公告)号：US20240006357A1

公开(公告)日：2024-01-04

申请号：US18465994

申请日：2023-09-13

申请人： ROHM CO., LTD.

发明人： Takayuki OSAWA

IPC分类号： H01L23/00 ,  H01L27/06 ,  H01L23/29

CPC分类号： H01L24/06 ,  H01L2924/10272 ,  H01L24/37 ,  H01L24/45 ,  H01L24/73 ,  H01L23/293 ,  H01L2224/0601 ,  H01L2224/061 ,  H01L2224/3702 ,  H01L2224/4502 ,  H01L2224/73101 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/12036 ,  H01L27/0629

摘要： This semiconductor device is provided with: a semiconductor layer; a cell that is provided on the semiconductor layer; an insulating film that covers the cell; a main electrode part that is superposed on the insulating film; a temperature-sensitive diode for sensing temperatures, the diode having a first electrode and a second electrode; and a connection electrode for diode, the connection electrode being used for the purpose of connecting the first electrode to the outside. The main electrode part has: a first bonding region to which a first conductive member is bonded; and a second bonding region to which a second conductive member is bonded. When viewed from the thickness direction of the semiconductor layer, the cell is provided on both a first semiconductor region in the semiconductor layer, and a second semiconductor region in the semiconductor layer.

公开(公告)号：US20230245988A1

公开(公告)日：2023-08-03

申请号：US18058006

申请日：2022-11-22

申请人： Apple Inc.

发明人： Kwan-Yu Lai ,  Kunzhong Hu ,  Jun Zhai ,  Young Doo Jeon

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/73 ,  H01L24/13 ,  H01L24/20 ,  H01L24/19 ,  H01L24/14 ,  H01L2224/73101 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/19 ,  H01L2224/11002 ,  H01L2224/11916 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/1184 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13018 ,  H01L2224/13075 ,  H01L2224/13541 ,  H01L2224/13552 ,  H01L2224/13575 ,  H01L2924/35121

摘要： Die reconstitution methods and dies with reconstituted contact bumps are described. In an embodiment, a die reconstitution method includes reconstituting a plurality of dies including first contact bumps of a first type, partially removing the first contact bumps, and forming second contact bumps of a second type on top of the partially removed first contact bumps, where the second type is different than the first type.

公开(公告)号：US20240105658A1

公开(公告)日：2024-03-28

申请号：US17935613

申请日：2022-09-27

申请人： NXP B.V.

发明人： Tsung Nan Lo ,  Antonio Aguinaldo Marquez Macatangay

IPC分类号： H01L23/00

CPC分类号： H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/13 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24991 ,  H01L2224/73101 ,  H01L2924/35121

摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over a semiconductor die, a portion of the RDL contacting a die pad of the semiconductor die. A non-conductive layer is formed over the RDL. An opening in the non-conductive layer is formed exposing a portion of the RDL. A plurality of plateau regions is formed in the non-conductive layer. A cavity region in the non-conductive layer separates each plateau region of the plurality of plateau regions. A metal layer is deposited over the non-conductive layer and exposed portion of the RDL and etched to expose the plurality of plateau regions through the metal layer. The cavity region remains substantially filled by a portion of the metal layer.

公开(公告)号：US11908825B2

公开(公告)日：2024-02-20

申请号：US17497368

申请日：2021-10-08

申请人： SK hynix Inc.

发明人： Jeong Hyun Park

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/49 ,  H01L24/20 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/2101 ,  H01L2224/48147 ,  H01L2224/4912 ,  H01L2224/49051 ,  H01L2224/49109 ,  H01L2224/49112 ,  H01L2224/73101 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2924/301

摘要： A semiconductor package includes a lower semiconductor die and an upper semiconductor die which are stacked with an offset in a first direction, wherein the lower semiconductor die includes a plurality of lower pads arranged in a second direction, which is perpendicular to the first direction, and wherein the upper semiconductor die includes a plurality of upper pads arranged in the second direction. The semiconductor package also includes bent wires electrically connecting the lower pads of the lower semiconductor die with the upper pads of the upper semiconductor die in the first direction. The semiconductor package further includes vertical wires such that a vertical wire is disposed on any one of the lower pad and the upper pad for each pair of pads electrically connected by a bent wire.

公开(公告)号：US20150380367A1

公开(公告)日：2015-12-31

申请号：US14717606

申请日：2015-05-20

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Fucheng CHEN

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02175 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0381 ,  H01L2224/03831 ,  H01L2224/04 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/06505 ,  H01L2224/08058 ,  H01L2224/08111 ,  H01L2224/08145 ,  H01L2224/10145 ,  H01L2224/1148 ,  H01L2224/1181 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/27831 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73101 ,  H01L2224/73104 ,  H01L2224/73201 ,  H01L2224/73204 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/81948 ,  H01L2224/83011 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2224/05 ,  H01L2224/13 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2224/80 ,  H01L2924/00

摘要： A chip includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a first dielectric region and a second dielectric region surrounding an outer periphery of the first dielectric region. A top surface of the first dielectric region is disposed below a top surface of the second dielectric region. The chip further includes a metal pad disposed in a through-hole in the first dielectric region and contacting a portion of the substrate.

摘要翻译： 芯片包括衬底和设置在衬底上的电介质层。 电介质层包括第一电介质区域和围绕第一电介质区域的外围的第二电介质区域。 第一电介质区域的顶表面设置在第二电介质区域的顶表面下方。 芯片还包括设置在第一电介质区域中的通孔中并与衬底的一部分接触的金属焊盘。