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公开(公告)号：US20210240393A1
公开(公告)日：2021-08-05
申请号：US17129185
申请日：2020-12-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： MYUNG HYUN JO , YOUNGWOOK KIM , JINWOO KIM , JAEYONG JEONG
Abstract: An operation method of a storage device including first and second physical functions respectively corresponding to first and second hosts includes receiving performance information from each of the first and second hosts, setting a first weight value corresponding to the first physical function and a second weight value corresponding to the second physical function, based on the received performance information, selecting one of a first submission queue, a second submission queue, a third submission queue, and a fourth submission queue based on an aggregated value table, the first and second submission queues being managed by the first host and the third and fourth submission queues are managed by the second host, processing a command from the selected submission queue, and updating the aggregated value table based on a weight value corresponding to the processed command from among the first and second weights and input/output (I/O) information of the processed command.
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2.发明申请公开(公告)号：US20170358361A1
公开(公告)日：2017-12-14
申请号：US15687564
申请日：2017-08-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： HYUN-WOOK PARK , KITAE PARK , JAEYONG JEONG
CPC classification number: G11C16/14 , G11C11/56 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3418 , G11C16/3445
Abstract: An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.
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3.发明公开公开(公告)号：US20230178154A1
公开(公告)日：2023-06-08
申请号：US18103754
申请日：2023-01-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： WON-TAECK JUNG , SANG-WAN NAM , JINWOO PARK , JAEYONG JEONG
CPC classification number: G11C16/20 , G11C16/08 , G11C16/3427 , G11C16/0483 , G11C16/10 , H10B41/27
Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
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公开(公告)号：US20150155048A1
公开(公告)日：2015-06-04
申请号：US14617976
申请日：2015-02-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JAEYONG JEONG , JU SEOK LEE
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/24 , G11C16/3454
Abstract: A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode.
Abstract translation: 非易失性存储器件包括连接到全位线结构中的多个位线的单元阵列，连接到多个位线的寻址缓冲器电路以及被配置为控制页缓冲器电路的控制逻辑。 控制逻辑控制页面缓冲电路以在第一读取模式中感测与选定页面的偶数和偶数列对应的存储器单元，并且读取对应于偶数和奇数列之一的存储器单元 的第二读取模式。 在第一读取模式下执行感测操作至少两次，并且在第二读取模式中执行一次感测操作。
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Patent Agency Ranking
公开(公告)号：US20220326890A1
公开(公告)日：2022-10-13
申请号：US17852652
申请日：2022-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： MYUNG HYUN JO , YOUNGWOOK KIM , JINWOO KIM , JAEYONG JEONG
Abstract: An operation method of a storage device including first and second physical functions respectively corresponding to first and second hosts includes receiving performance information from each of the first and second hosts, setting a first weight value corresponding to the first physical function and a second weight value corresponding to the second physical function, based on the received performance information, selecting one of a first submission queue, a second submission queue, a third submission queue, and a fourth submission queue based on an aggregated value table, the first and second submission queues being managed by the first host and the third and fourth submission queues are managed by the second host, processing a command from the selected submission queue, and updating the aggregated value table based on a weight value corresponding to the processed command from among the first and second weights and input/output (I/O) information of the processed command.
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6.发明申请公开(公告)号：US20180374541A1
公开(公告)日：2018-12-27
申请号：US15911208
申请日：2018-03-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： WON-TAECK JUNG , SANG-WAN NAM , JINWOO PARK , JAEYONG JEONG
CPC classification number: G11C16/20 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3427 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
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7.发明申请公开(公告)号：US20140153330A1
公开(公告)日：2014-06-05
申请号：US14088511
申请日：2013-11-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： HYUN JUN YOON , JAEYONG JEONG , MYUNG-HOON CHOI , KITAE PARK
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3404 , G11C16/3422
Abstract: An operating method for a non-volatile memory device includes applying first and second read voltages to a first word line to perform a read operation; counting first memory cells each having a threshold voltage belonging to a first voltage range between the first read voltage and the second read voltage; applying a third read voltage to the first word line sequentially after applying the second read voltage to count second memory cells each having a second threshold voltage belonging to a voltage range between the second read voltage and the third read voltage; comparing the number of first memory cells counted and the number of second memory cells counted; determining a fourth read voltage based on a result of the comparing; and applying the fourth read voltage to the first word line sequentially after applying the third read voltage.
Abstract translation: 一种用于非易失性存储器件的操作方法包括：将第一和第二读取电压施加到第一字线以执行读取操作; 计数每个具有属于第一读取电压和第二读取电压之间的第一电压范围的阈值电压的第一存储器单元; 在施加第二读取电压以对具有属于第二读取电压和第三读取电压之间的电压范围的第二阈值电压的第二存储器单元计数时，顺序地向第一字线施加第三读取电压; 比较计数的第一存储器单元的数量和计数的第二存储单元的数量; 基于所述比较的结果确定第四读取电压; 以及在施加第三读取电压之后，将第四读取电压顺序地施加到第一字线。
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8.发明申请公开(公告)号：US20220068397A1
公开(公告)日：2022-03-03
申请号：US17523385
申请日：2021-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： WON-TAECK JUNG , SANG-WAN NAM , JINWOO PARK , JAEYONG JEONG
Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
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公开(公告)号：US20150117100A1
公开(公告)日：2015-04-30
申请号：US14336343
申请日：2014-07-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： HYUN-WOOK PARK , JUNG-SOO KIM , JAEYONG JEONG , KITAE PARK , YOUNGSUN SONG
IPC: G11C16/10
CPC classification number: G11C16/225 , G11C16/0483 , G11C16/10
Abstract: A method of programming a storage device comprises determining whether at least one open page exists in a memory block of a nonvolatile memory device, and as a consequence of determining that at least one open page exists in the memory block, closing the at least one open page through a dummy pattern program operation, and thereafter performing a continuous writing operation on the memory block.
Abstract translation: 一种对存储设备进行编程的方法包括确定至少一个开放页面是否存在于非易失性存储器件的存储器块中，并且作为确定存储器块中存在至少一个打开页面的结果，关闭至少一个打开的 通过虚拟图案编程操作，然后对存储块进行连续写入操作。
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