公开(公告)号：US20240046993A1

公开(公告)日：2024-02-08

申请号：US18170893

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOHYUN KANG ,  JIN-YOUNG KIM ,  HYUNA KIM ,  SE HWAN PARK ,  YOUNGDEOK SEO ,  HYUNKYO OH ,  HEEWON LEE ,  DONGHOO LIM

IPC: G11C16/12 ,  G11C16/26 ,  G06F11/10

CPC classification number: G11C16/12 ,  G11C16/26 ,  G06F11/1044

Abstract: A method of operating a non-volatile memory device, which is configured to communicate with a storage controller includes: receiving a first request indicating a read reclaim determination and including environment information from the storage controller, performing a first on-chip read operation for generating first distribution information based on the first request, determining whether a read reclaim is required based on the first distribution information, and providing the storage controller with a determination result having a first bit value in response to determining that the read reclaim is required.

公开(公告)号：US20190385681A1

公开(公告)日：2019-12-19

申请号：US16442672

申请日：2019-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SE-WON YUN ,  JIN-YOUNG KIM ,  IL-HAN PARK ,  HYUN SEO ,  BONG-SOON LIM

IPC: G11C16/16 ,  G11C16/04

Abstract: A memory device includes an array of vertical NAND strings of nonvolatile memory cells, on an underlying substrate. An erase control circuit is provided, which is configured to drive a plurality of bit lines electrically coupled to the array of vertical NAND strings of nonvolatile memory cells with respective erase voltages having unequal magnitudes during an operation to erase the nonvolatile memory cells in the array of vertical NAND strings. This erase control circuit may also be configured to drive a first of the plurality of bit lines with a first erase voltage for a first duration and drive a second of the plurality of bit lines with a second erase voltage for a second duration unequal to the first duration during the operation to erase the nonvolatile memory cells in the array of vertical NAND strings.

公开(公告)号：US20190088337A1

公开(公告)日：2019-03-21

申请号：US16191656

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNE-HONG PARK ,  KI-WHAN SONG ,  BONG-SOON LIM ,  SU-CHANG JEON ,  JIN-YOUNG KIM ,  CHANG-YEON YU ,  DONG-KYO SHIM ,  SEONG-JIN KIM

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C7/1084 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.

公开(公告)号：US20230125101A1

公开(公告)日：2023-04-27

申请号：US18088046

申请日：2022-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANGHO CHOI ,  JIN-YOUNG KIM ,  SE HWAN PARK ,  IL HAN PARK ,  JI-SANG LEE ,  JOONSUC JANG

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

公开(公告)号：US20210027835A1

公开(公告)日：2021-01-28

申请号：US16821265

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DOJEON LEE ,  DUEUNG KIM ,  JIN-YOUNG KIM

IPC: G11C11/56 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074

Abstract: A memory device includes a bay comprises a plurality of word lines, a plurality of bit lines, and a memory cell connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines, a row decoder configured to bias at least one word line of the word lines adjacent to the first word line and float remaining non-adjacent word lines of the plurality of word lines not adjacent to the first word line, in an access operation associated with the memory cell, and a column decoder configured to bias at least one bit line of the bit lines adjacent to the first bit line and float remaining non-adjacent bit lines of the plurality of bit lines not adjacent to the first bit line, in the access operation.

公开(公告)号：US20200050400A1

公开(公告)日：2020-02-13

申请号：US16292769

申请日：2019-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-YOUNG KIM ,  JAE-DUK YU ,  YU-HUN JUN

IPC: G06F3/06

Abstract: A method of accessing data in a storage device including first and second nonvolatile memories of different types is provided. The method includes setting a meta data attribute table by classifying a plurality of meta data based on a plurality of data attributes and accessible memory types, detecting a data attribute of first meta data among the plurality of meta data based on the meta data attribute table in response to receiving a first access request for the first meta data, determining a target memory optimized for the first meta data from among the first and second nonvolatile memories based on the detected data attribute of the first meta data, and performing an access operation on the target memory based on the first meta data. The plurality of meta data are used for controlling an operation of the storage device.

公开(公告)号：US20220101930A1

公开(公告)日：2022-03-31

申请号：US17359688

申请日：2021-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANGHO CHOI ,  JIN-YOUNG KIM ,  SE HWAN PARK ,  IL HAN PARK ,  JI-SANG LEE ,  JOONSUC JANG

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

公开(公告)号：US20200034047A1

公开(公告)日：2020-01-30

申请号：US16458692

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-DUK YU ,  JIN-YOUNG KIM ,  YU-HUN JUN

IPC: G06F3/06 ,  G06F13/16

Abstract: A solid state drive and a method for accessing the metadata are provided. The solid state drive includes different kinds of first and second memories and a memory controller which controls the first and second memories, wherein the memory controller receives a metadata access request from a host, and includes a condition checker which determines conditions of the first and second memories in response to the metadata access request and selects at least one of the conditions, and the memory controller accesses to the memory selected by the condition checker.

公开(公告)号：US20180226128A1

公开(公告)日：2018-08-09

申请号：US15717992

申请日：2017-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNE-HONG PARK ,  KI-WHAN SONG ,  BONG-SOON LIM ,  SU-CHANG JEON ,  JIN-YOUNG KIM ,  CHANG-YEON YU ,  DONG-KYO SHIM ,  SEONG-JIN KIM

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.