公开(公告)号：US20190172865A1

公开(公告)日：2019-06-06

申请号：US15996480

申请日：2018-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGHOE CHO ,  JONGBO SHIM ,  SEUNGHOON YEON ,  WON IL LEE

IPC: H01L27/146

Abstract: A method of manufacturing a semiconducor device includes providing a semiconductor substrate having a top surface, on which has been formed a color filter and a micro-lens, and a bottom surface opposite to the top surface, forming a redistribution line on the bottom surface of the semiconductor substrate, and forming on the bottom surface of the semiconductor substrate a passivation layer covering the redistribution line. After the redistribution line and passivation layer are formed, an oxide layer between the redistribution line and the passivation is formed at a temperature that avoids thermal damage to the color filter and the micro-lens.

公开(公告)号：US20210043612A1

公开(公告)日：2021-02-11

申请号：US16845567

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： JANGWOO LEE ,  JONGBO SHIM ,  JI HWANG KIM ,  YUNGCHEOL KONG ,  YOUNGBAE KIM ,  TAEHWAN KIM ,  HYUNGLAK MA

IPC: H01L25/10 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package device may include a first package substrate, a first semiconductor chip on the first package substrate, an interposer on the first semiconductor chip, a warpage prevention member on the interposer, a molding member on the interposer and the first package substrate, and a second package substrate on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.

公开(公告)号：US20190333957A1

公开(公告)日：2019-10-31

申请号：US16507623

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  CHAJEA JO ,  HYOEUN KIM ,  JONGBO SHIM ,  SANG-UK HAN

IPC: H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US20220319973A1

公开(公告)日：2022-10-06

申请号：US17807894

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  HYUNKYU KIM ,  JONGBO SHIM ,  EUNHEE JUNG ,  KYOUNGSEI CHOI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US20200020637A1

公开(公告)日：2020-01-16

申请号：US16432551

申请日：2019-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  KILSOO KIM ,  JONGBO SHIM ,  JANGWOO LEE ,  EUNHEE JUNG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a substrate, a semiconductor chip mounted on the substrate, an interposer chip on the semiconductor chip and including a redistribution pattern, a first pad on the interposer chip, a second pad on the interposer chip and spaced apart from the first pad, and a bonding wire electrically connected to the second pad and the first substrate. The second pad is electrically connected through the redistribution pattern to the first pad. The footprint of the interposer chip is greater than the footprint of the first semiconductor chip.

公开(公告)号：US20230402357A1

公开(公告)日：2023-12-14

申请号：US18133105

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGBO SHIM ,  JI-YONG PARK

IPC: H01L23/498 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L23/49811 ,  H01L23/49822 ,  H01L23/3128 ,  H10B80/00 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package includes a first redistribution substrate, a semiconductor chip on the first redistribution substrate, and vertical conductive structures spaced apart from a side surface of the semiconductor chip. Each of the vertical conductive structures includes a wire, and a metal layer covering a side surface of the wire. A top surface of the wire is exposed from the metal layer.

公开(公告)号：US20210407923A1

公开(公告)日：2021-12-30

申请号：US17167789

申请日：2021-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHO KIM ,  JONGBO SHIM ,  HWAN PIL PARK ,  CHOONGBIN YIM ,  JUNGWOO KIM

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.

公开(公告)号：US20240079250A1

公开(公告)日：2024-03-07

申请号：US18118303

申请日：2023-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEWON CHOI ,  JONGBO SHIM

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2924/1432 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042

Abstract: A method of manufacturing a semiconductor package includes; positioning a passive element on an upper insulating layer of a package substrate, wherein the upper insulating layer of the package substrate exposes upper surfaces of first substrate pads and second substrate pads, the passive element includes; electrodes on respective corners of a lower surface of the passive element, solder members respectively on the electrodes, and an insulating spacer on a central portion of the lower surface of the passive element between the solder members, and the solder members are respectively disposed on the second substrate pads. The method further includes; bonding the passive element on the package substrate through the solder members and the second substrate pads, and bonding a semiconductor device to the first substrate pads on the package substrate through conductive bumps on a lower surface of the semiconductor device, wherein the semiconductor device is laterally spaced apart from the passive element on the package substrate.

公开(公告)号：US20230260891A1

公开(公告)日：2023-08-17

申请号：US18308433

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  HYUNKYU KIM ,  JONGBO SHIM ,  EUNHEE JUNG ,  KYOUNGSEL CHOI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/45 ,  H01L25/0657

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US20220115281A1

公开(公告)日：2022-04-14

申请号：US17350329

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  DONGHO KIM ,  JIN-WOO PARK ,  JONGBO SHIM

IPC: H01L23/13 ,  H01L25/10 ,  H01L21/48 ,  H01L25/00

Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate. wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.