公开(公告)号：US09859376B2

公开(公告)日：2018-01-02

申请号：US14977865

申请日：2015-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-ki Lee ,  Jae-Young Park ,  Dong-Hun Lee ,  Bon-Young Koo ,  Sun-Young Lee ,  Jae-Jong Han

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775

CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.

公开(公告)号：US09202844B2

公开(公告)日：2015-12-01

申请号：US13966423

申请日：2013-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jong Han ,  Yoon-Goo Kang ,  Won-Seok Yoo ,  Kong-Soo Lee ,  Han-Jin Lim ,  Seong-Hoon Jeong

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.

Abstract translation: 半导体器件包括在具有第一导电型杂质的衬底上的具有第二导电类型杂质的下互连。 开关装置在较低的互连上。 第一阻挡层设置在下互连和开关器件之间。 第一阻挡层包括碳（C），锗（Ge）或其组合。 第二阻挡层可以设置在基板和下部互连件之间。

公开(公告)号：US08987694B2

公开(公告)日：2015-03-24

申请号：US13729742

申请日：2012-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jong Han ,  Kong-Soo Lee ,  Yoon-Goo Kang ,  Ho-Kyun An ,  Seong-Hoon Jeong

IPC: H01L29/02 ,  H01L45/00 ,  H01L27/102 ,  H01L27/24 ,  H01L27/10

CPC classification number: H01L45/04 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/124 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144

Abstract: Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.

Abstract translation: 半导体器件及其制造方法包括半导体衬底中的场区以限定有源区。 层间绝缘层位于半导体衬底上。 半导体图案在垂直延伸穿过层间绝缘层的孔内。 半导体图案与有源区域接触。 阻挡区域在半导体图案和层间绝缘层之间。 阻挡区域包括第一缓冲介电材料和阻挡介电材料。 第一缓冲电介质材料在阻挡介电材料和半导体图案之间，并且阻挡介电材料与半导体图案和有源区两者间隔开。