公开(公告)号：US20190081174A1

公开(公告)日：2019-03-14

申请号：US16044584

申请日：2018-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-GUN YOU ,  Chang-Hee Kim ,  Sung-II Park ,  Dong-Hun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L23/532 ,  H01L21/308 ,  H01L21/8238

Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

公开(公告)号：US10191554B2

公开(公告)日：2019-01-29

申请号：US14657462

申请日：2015-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-seok Lee ,  Dong-Hun Lee

IPC: G06F3/01 ,  G06K9/00 ,  G06F3/03 ,  G06F3/0484

Abstract: A display apparatus and a controlling method thereof are provided. The controlling method of a display apparatus includes displaying a mode conversion user interface (UI) that provides a guideline to enter a motion task mode; recognizing a first motion that corresponds to the guideline; entering the motion task mode that enables a second motion to control a function of the display apparatus in response to the first motion being recognized while the guideline is displayed on the display apparatus; and displaying a motion task UI to perform the motion task mode.

公开(公告)号：US10944003B2

公开(公告)日：2021-03-09

申请号：US16816908

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gun You ,  Chang-Hee Kim ,  Sung-Il Park ,  Dong-Hun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238 ,  H01L23/532 ,  H01L21/308 ,  H01L29/423 ,  H01L29/165 ,  H01L21/8234

Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

公开(公告)号：US09859376B2

公开(公告)日：2018-01-02

申请号：US14977865

申请日：2015-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-ki Lee ,  Jae-Young Park ,  Dong-Hun Lee ,  Bon-Young Koo ,  Sun-Young Lee ,  Jae-Jong Han

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775

CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.

公开(公告)号：US10937700B2

公开(公告)日：2021-03-02

申请号：US15583167

申请日：2017-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Yun-Il Lee ,  Hyung-Suk Lee ,  Yeon-Cheol Heo ,  Byoung-Gi Kim ,  Chang-Min Yoe ,  Seung-Chan Yun ,  Dong-Hun Lee

IPC: H01L27/082 ,  H01L27/24 ,  H01L27/115 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L29/786 ,  H01L27/088 ,  H01L29/161 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78

Abstract: A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.

公开(公告)号：US09978431B2

公开(公告)日：2018-05-22

申请号：US14819978

申请日：2015-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wun-Ki Jung ,  Min-Ho Kwon ,  Kwi-Sung Yoo ,  Won-Ho Choi ,  Dong-Hun Lee ,  Seog-Heon Ham

IPC: G11C7/06 ,  G11C7/10 ,  H01L27/146 ,  G11C7/22 ,  G11C19/00 ,  G11C27/02

CPC classification number: G11C7/06 ,  G11C7/10 ,  G11C7/1033 ,  G11C7/1051 ,  G11C7/22 ,  G11C19/00 ,  G11C27/02 ,  H01L27/146 ,  H01L27/14634 ,  H01L27/14643

Abstract: A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

公开(公告)号：US09520297B2

公开(公告)日：2016-12-13

申请号：US15099067

申请日：2016-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun Lee ,  Sunhom Steve Paak

IPC: H01L21/336 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762

CPC classification number: H01L21/3085 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes sequentially forming a hard mask layer and a first sacrificial layer on a substrate, forming a first mandrel on the first sacrificial layer, forming a first spacer on both sidewalls of the first mandrel, removing the first mandrel, forming a second mandrel by etching the first sacrificial layer using the first spacer as an etch mask, forming a second spacer on both sidewalls of the second mandrel, removing the second mandrel, forming a hard mask pattern by patterning the hard mask layer using the second spacer as an etch mask, the hard mask pattern including first to ninth fin-type mask patterns extending to be parallel with each other in a first direction and sequentially spaced apart from each other in a second direction perpendicular to the first direction, removing the third, fifth and seventh fin-type mask patterns, forming first to sixth active patterns by etching the substrate using the hard mask pattern as an etch mask, and forming a first gate electrode extending in the second direction to intersect the first to fourth active patterns and a second gate electrode extending in the second direction to intersect the third to sixth active patterns and spaced apart from the first gate electrode in the first direction without intersecting the first and second active patterns.

Abstract translation: 形成半导体器件的方法包括在衬底上依次形成硬掩模层和第一牺牲层，在第一牺牲层上形成第一芯棒，在第一芯棒的两个侧壁上形成第一间隔物，去除第一芯棒， 通过使用第一间隔物作为蚀刻掩模蚀刻第一牺牲层来形成第二心轴，在第二心轴的两个侧壁上形成第二间隔物，去除第二心轴，通过使用第二心轴图案化硬掩模层形成硬掩模图案 间隔物作为蚀刻掩模，所述硬掩模图案包括延伸为在第一方向上彼此平行并且在垂直于所述第一方向的第二方向上彼此间隔开的第一至第九鳍式掩模图案， 第五和第七鳍型掩模图案，通过使用硬掩模图案作为蚀刻掩模蚀刻衬底来形成第一至第六有源图案，以及fo 将在第二方向上延伸以与第一至第四有源图案相交的第一栅极电极和第二栅电极沿第二方向延伸以与第三至第六有源图案相交并且在第一方向上与第一栅电极间隔开而不相交 第一和第二活动模式。

公开(公告)号：US09135963B2

公开(公告)日：2015-09-15

申请号：US13757977

申请日：2013-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wun-Ki Jung ,  Min-Ho Kwon ,  Kwi-Sung Yoo ,  Won-Ho Choi ,  Dong-Hun Lee ,  Seog-Heon Ham

IPC: H01L27/00 ,  H03F3/08 ,  H01J40/14 ,  G11C7/06 ,  G11C7/10 ,  H01L27/146 ,  G11C19/00 ,  G11C27/02

CPC classification number: G11C7/06 ,  G11C7/10 ,  G11C7/1033 ,  G11C7/1051 ,  G11C7/22 ,  G11C19/00 ,  G11C27/02 ,  H01L27/146 ,  H01L27/14634 ,  H01L27/14643

Abstract: A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

Abstract translation: 行存储器件包括多个存储单元，数据线对，读出放大器和输出单元。 多个存储单元被一行地相邻配置。 数据线对耦合到存储器单元以将存储在存储器单元中的存储器数据位顺序传送到读出放大器。 读出放大器被配置为放大通过数据线对顺序传送的存储器数据位，相应的延迟时间彼此不同。 输出单元对读出放大器的输出进行采样，以响应读取的时钟信号顺序地输出存储器数据位的重新定时数据位。 读取时钟信号具有小于延迟时间之间的最大延迟时间的循环周期。

公开(公告)号：US20160307767A1

公开(公告)日：2016-10-20

申请号：US15099067

申请日：2016-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun Lee ,  Sunhom Steve Paak

IPC: H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L21/3085 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes sequentially forming a hard mask layer and a first sacrificial layer on a substrate, forming a first mandrel on the first sacrificial layer, forming a first spacer on both sidewalls of the first mandrel, removing the first mandrel, forming a second mandrel by etching the first sacrificial layer using the first spacer as an etch mask, forming a second spacer on both sidewalls of the second mandrel, removing the second mandrel, forming a hard mask pattern by patterning the hard mask layer using the second spacer as an etch mask, the hard mask pattern including first to ninth fin-type mask patterns extending to be parallel with each other in a first direction and sequentially spaced apart from each other in a second direction perpendicular to the first direction, removing the third, fifth and seventh fin-type mask patterns, forming first to sixth active patterns by etching the substrate using the hard mask pattern as an etch mask, and forming a first gate electrode extending in the second direction to intersect the first to fourth active patterns and a second gate electrode extending in the second direction to intersect the third to sixth active patterns and spaced apart from the first gate electrode in the first direction without intersecting the first and second active patterns.

Abstract translation: 形成半导体器件的方法包括在衬底上依次形成硬掩模层和第一牺牲层，在第一牺牲层上形成第一芯棒，在第一芯棒的两个侧壁上形成第一间隔物，去除第一芯棒， 通过使用第一间隔物作为蚀刻掩模蚀刻第一牺牲层来形成第二心轴，在第二心轴的两个侧壁上形成第二间隔物，去除第二心轴，通过使用第二心轴图案化硬掩模层形成硬掩模图案 间隔物作为蚀刻掩模，所述硬掩模图案包括延伸为在第一方向上彼此平行并且在垂直于所述第一方向的第二方向上彼此间隔开的第一至第九鳍式掩模图案， 第五和第七鳍型掩模图案，通过使用硬掩模图案作为蚀刻掩模蚀刻衬底来形成第一至第六有源图案，以及fo 将在第二方向上延伸以与第一至第四有源图案相交的第一栅极电极和第二栅电极沿第二方向延伸以与第三至第六有源图案相交并且在第一方向上与第一栅电极间隔开而不相交 第一和第二活动模式。

公开(公告)号：US09258506B2

公开(公告)日：2016-02-09

申请号：US14335309

申请日：2014-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hun Shin ,  Chang-Eun Kang ,  Won-Ho Choi ,  Dong-Hun Lee

IPC: H04N5/335 ,  H04N5/378 ,  H03K21/38 ,  H03K23/66 ,  H03M1/14 ,  H03M1/12 ,  H03M1/56 ,  H04N5/357 ,  H04N5/369 ,  H04N5/3745 ,  H04N13/02

CPC classification number: H04N5/378 ,  H03K21/38 ,  H03K23/667 ,  H03M1/123 ,  H03M1/14 ,  H03M1/56 ,  H04N5/3575 ,  H04N5/3696 ,  H04N5/3745 ,  H04N13/243 ,  H04N13/254 ,  H04N13/271 ,  H04N2213/001

Abstract: A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

Abstract translation: 计数器电路包括第一计数器和第二计数器。 第一计数器被配置为响应于基于第一比较的第一计数使能信号来计数与第一频率切换的第一计数器时钟信号，以产生N位计数器输出信号的上（N-M）位信号 信号在粗计数间隔期间。 N和M是自然数，N大于M，M大于或等于3.第二计数器被配置为对第二计数器时钟信号进行计数，第二计数器时钟信号与第二频率相交换，第二频率高于第一频率以产生 响应于基于第一比较信号的第二计数使能信号和在粗计数间隔之后的精细计数间隔期间的第二比较信号，N比特计数器输出信号的较低M比特信号。